DSPIC33FJ32GS608 datasheet(311/416 Pages) MICROCHIP

311 / 416 page

 2009 Microchip Technology Inc.

Preliminary

DS70591B-page 311

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

ADCON: A/D CONTROL REGISTER

R/W-0

U-0

R/W-0

U-0

R/W-0

U-0

R/W-0

ADON

—

ADSIDL

SLOWCLK(1)

—GSWTRG

—FORM(1)

bit 15

bit 8

R/W-0

U-0

R/W-0

R/W-1

EIE(1)

ORDER(1)

SEQSAMP(1) ASYNCSAMP(1)

—

ADCS<2:0>(1)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

ADON: A/D Operating Mode bit

1 = A/D converter module is operating

0 = A/D converter is off

bit 14

Unimplemented: Read as ‘0’

bit 13

ADSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12

SLOWCLK: Enable The Slow Clock Divider bit(1)

1 = ADC is clocked by the auxiliary PLL (ACLK)

0 = ADC is clock by the primary PLL (FVCO)

bit 11

Unimplemented: Read as ‘0’

bit 10

GSWTRG: Global Software Trigger bit

When this bit is set by the user, it will trigger conversions if selected by the TRGSRC<4:0> bits in the

ADCPCx registers. This bit must be cleared by the user prior to initiating another global trigger (i.e., this

bit is not auto-clearing).

bit 9

Unimplemented: Read as ‘0’

bit 8

FORM: Data Output Format bit(1)

1 = Fractional (DOUT = dddd dddd dd00 0000)

0 = Integer (DOUT = 0000 00dd dddd dddd)

bit 7

EIE: Early Interrupt Enable bit(1)

1 = Interrupt is generated after first conversion is completed

0 = Interrupt is generated after second conversion is completed

bit 6

ORDER: Conversion Order bit(1)

1 = Odd numbered analog input is converted first, followed by conversion of even numbered input

0 = Even numbered analog input is converted first, followed by conversion of odd numbered input

bit 5

SEQSAMP: Sequential Sample Enable bit(1)

1 = Shared Sample and Hold (S&H) circuit is sampled at the start of the second conversion if

ORDER = 0. If ORDER = 1, then the shared S&H is sampled at the start of the first conversion.

0 = Shared S&H is sampled at the same time the dedicated S&H is sampled if the shared S&H is not

currently busy with an existing conversion process. If the shared S&H is busy at the time the

dedicated S&H is sampled, then the shared S&H will sample at the start of the new conversion

cycle.

bit 4

ASYNCSAMP: Asynchronous Dedicated S&H Sampling Enable bit(1)

1 = The dedicated S&H is constantly sampling and then terminates sampling as soon as the trigger

pulse is detected.

0 = The dedicated S&H starts sampling when the trigger event is detected and completes the sampling

process in two ADC clock cycles.

Note 1: This control bit can only be changed while the ADC is disabled (ADON = 0).

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