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SFSL4.5MDB Datasheet(PDF) 4 Page - Yamar Electronics Ltd.

Part # SFSL4.5MDB
Description  Smart Slave for DC-BUS Powerline Network
PDF  15 Pages
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Manufacturer  YAMAR [Yamar Electronics Ltd.]
Direct Link  http://www.yamar.com
Logo YAMAR - Yamar Electronics Ltd.

SFSL4.5MDB Datasheet(HTML) 4 Page - Yamar Electronics Ltd.

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Preliminary and proprietary Information of YAMAR Electronics Ltd. Subject to change without notice.
© 2010 Yamar Electronics Ltd.
4
DS-SIG61 R0.932
OscIn
53
Analog
Input
Crystal Input
RxN
9
Analog
Output
The internal comparator negative pin. Its value is internally pulled to
Vdd/2. Bypass RxN to Ground with a 1nF capacitor.
RxP
61
Analog
Input
Positive pin input signal. Should be tied to RxN with a 1K Ohm
resistor.
DTxO
45
Tristate/
Output
2mA
Modulated digital transmit signal output to both ceramic filters.
RxIn
10
Analog
Input
Receive input
from the DC-BUS to the RX operational amplifier. This
input is pulled internally to Vdd/2.
TxO
8
Analog
Output
Transmit output.
F0B
59
Analog, Bi
directional
F0 External filter I/O. Its value is internally pulled to Vdd/2.
F1B
58
Analog, Bi
directional
F1 External filter I/O. Its value is internally pulled to Vdd/2.
TxOn
20
Output
12mA
HIGH when the device is transmitting a message.
RxOn
17
Output
12mA
HIGH when the device is in receive mode.
I/O Signals
In0
47
Input PD
The pin is read by the Master with a Read or Read-Change
command.
In1
44
Input PD
The pin is read by the Master with a Read or Read-Change
command.
In2_HDI
42
Input
The pin is read by the Master with a Read or Read-Change
command. When in SIG60 mode, HDI input.
In3_HDC
41
Input
The pin is read by the Master with a Read or Read-Change
command. When in SIG60 mode, HDC input.
In4
40
Input PD
The pin is read by the Master with a Read or Read-Change
command.
In5
39
Input PD
The pin is read by the Master with a Read or Read-Change
command.
In6
37
Input PD
The pin is read by the Master with a Read or Read-Change
command.
In7
36
Input PD
The pin is read by the Master with a Read or Read-Change
command.
Out0
28
Output
8mA
Output of data bit 0 when the Write command received from Master.
Out1
27
Output
8mA
Output of data bit 1 when the Write command received from Master.
Out2
25
Output
8mA
Output of data bit 2 when the Write command received from Master.
Out3
24
Output
8mA
Output of data bit 3 when the Write command received from Master.
Out4
22
Output
8mA
Output of data bit 4 when the Write command received from Master.
Out5
21
Output
8mA
Output of data bit 5 when the Write command received from Master.
Out6
19
Output
8mA
Output of data bit 6 when the Write command received from Master.
Out7
18
Output
8mA
Output of data bit 7 when the Write command received from Master.
Configuration Signals
Id0
16
Input PD
SIG61 bit 0 ID address in the network.
Id1
14
Input PD
SIG61 bit 1 ID address in the network.
Id2
13
Input PD
SIG61 bit 2 ID address in the network.
Id3
12
Input PD
SIG61 bit 3 ID address in the network.



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