Preliminary and proprietary Information of YAMAR Electronics Ltd. Subject to change without notice.

© 2010 Yamar Electronics Ltd.

5

DS-SIG61 R0.932

F0F1-0

49

Input PD

Frequency selection pins. See 4.2.

F0F1-1

50

Input PD

Frequency selection pins. See 4.2.

F0F1-2

55

Input PD

Frequency selection pins. See 4.2.

F0F1-3

56

Input PD

Frequency selection pins. See 4.2.

BitRate0

1

Input PD

Bit rate selection pins. See 4.3.

BitRate1

2

Input PD

Bit rate selection pins. See 4.3.

NC

5

---

Not connected.

Mode2

48

Input PD

Should be left unconnected.

Mode3

62

Input PD

Should be connected to Vdd.

Mode4

36

Input PD

Should be connected to Vdd

AutoFreqCh

64

Input PD

Automatic Frequency Change. When HIGH, the device automatically

switches frequency after about 4 seconds without bus activity.

AutoSleep

30

Input PD

When this pin is set to HIGH, the device will automatically enter sleep

mode after about 8 seconds without bus activity.

F1nF0

38

Input PD

Selects between F0 / F1. HIGH – F1, LOW – F0

Power signals

Gnd

4,11,

34,43,

57

Power

Ground

Vdd

6,7,33,

46,51

Power

3.3V power supply.

AGnd

54

Power

Analog Ground

AVdd

60

Power

3.3V Analog Power. Separate from Vdd with a 10 Ohm resistor and bypass

to Ground with 1nF and 10nF capacitor.

Exp

Exp

May be connected to GND

PD – Pull down resistor 100K ohm ±%30

PU – Pull up resistor 100K ohm ±%30

Table 3.1 - Device signals

3.1 Power Signals

Vdd and Gnd layout traces should be as wide as possible. It is recommended to connect a 0.1uF

capacitor between each Vdd and ground pins, as close as possible to the pins.

Analog Vdd pin, AVdd, should be connected to Vdd. AGnd should be connected to ground. The Analog

supply has to be sufficiently powerful (capable of current driving), to avoid any fluctuations of supply

voltage level. It is recommended to keep the lines connecting the 3.3V power supply to Vdd pins as

short as possible with wide PCB traces.

R3

10

C5

1n

Vdd

C6

10n

AVdd

Figure 3.2 - Recommended AVdd circuitry