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IP4778CZ38/V Datasheet(PDF) 9 Page - NXP Semiconductors |
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IP4778CZ38/V Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 26 page ![]() IP4778CZ38_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 12 February 2009 9 of 26 NXP Semiconductors IP4778CZ38 HDMI ESD protection, DDC buffering and hot plug control [1] This parameter is guaranteed by design. [2] For level shifting N-FET. [3] This measurement is performed with a 0.1 µF external capacitor on pin TMDS_BIAS. [1] The ENABLE pin has to be connected permanently to VCC(3V3) if no enable control is needed. Table 6. CEC circuit VCC(3V3) = 2.7 V o 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Board side: input pin CEC_IN CI(ch-GND)(levsh) level shifting input capacitance from channel to ground VCC(3V3) = 0 V; f = 1 MHz; Vbias = 2.5 V [1] - 1216pF SRr rising slew rate VI > 1.8 V - 10 - mV/ µs N-FET ∆Von on-state voltage drop N-FET state = on; VCC(3V3) = 2.5 V; VS = GND; IDS =3mA [2] - 125 140 mV Connector side: output pin CEC_OUT ILI input leakage current −1 +0.1 +1 µA Rdyn dynamic resistance I = 1 A; IEC 61000-4-5/9 positive transient - 2.4 - Ω negative transient - 1.3 - Ω VCL(ch)trt(pos) positive transient channel clamping voltage VESD = 8 kV per IEC 61000-4-2; voltage 30 ns after trigger; Tamb =25 °C [3] -8 -V Table 7. Enable circuit VCC(3V3) = 2.7 V to 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Board side: input pin ENABLE[1] VIH HIGH-level input voltage HIGH = enable 0.7 × VCC(3V3) -VCC(5V0) + 0.5 V VIL LOW-level input voltage LOW = disable −0.5 - 0.3 × VCC(3V3) V IIL LOW-level input current VI = 0.2 V; VCC(3V3) = 5.5 V -10 - µA ILI input leakage current −1 +0.1 +1 µA Ci input capacitance VI = 3 V or 0 V - 3 7 pF Table 8. Hot Plug control circuit VCC(5V0) = 4.5 V to 5.5 V; VCC(3V3) = 2.7 V to 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Board side: input pin HOT_PLUG_DET_IN VIH HIGH-level input voltage HIGH = Hot Plug off 0.7 × V CC(3V3) -VCC(5V0) + 0.5 V VIL LOW-level input voltage LOW = Hot Plug on −0.5 - 0.3 × V CC(3V3) V IIL LOW-level input current VI = 2.0 V; VCC(3V3) = 5.5 V - 10 - µA ILI input leakage current −1 +0.1 +1 µA Ci input capacitance VI = 3 V or 0 V - 4 7 pF |
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