PIC16F707-ESLASHML datasheet(158/284 Pages) MICROCHIP

158 / 284 page

PIC16F707/PIC16LF707

DS41418A-page 158

Preliminary

 2010 Microchip Technology Inc.

FIGURE 19-2:

SPI MODE BLOCK

DIAGRAM

19.1.1

MASTER MODE

In Master mode, data transfer can be initiated at any

time because the master controls the SCK line. Master

mode determines when the slave (Figure 19-1,

Processor 2) transmits data via control of the SCK line.

19.1.1.1

Master Mode Operation

The SSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

first. The SSPBUF register holds the data that is written

out of the master until the received data is ready. Once

the eight bits of data have been received, the byte is

moved to the SSPBUF register. The Buffer Full Status

bit, BF of the SSPSTAT register, and the SSP Interrupt

Flag bit, SSPIF of the PIR1 register, are then set.

Any write to the SSPBUF register during transmission/

reception of data will be ignored and the Write Collision

Detect bit, WCOL of the SSPCON register, will be set.

User software must clear the WCOL bit so that it can be

determined if the following write(s) to the SSPBUF

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data is written to the SSPBUF. The BF bit of the

SSPSTAT register is set when SSPBUF has been

loaded with the received data (transmission is

complete). When the SSPBUF is read, the BF bit is

cleared. This data may be irrelevant if the SPI is only a

transmitter. The SSP interrupt may be used to

determine

when

the

transmission/reception

complete and the SSPBUF must be read and/or

written. If interrupts are not used, then software polling

can be done to ensure that a write collision does not

occur. Example 19-1 shows the loading of the SSPBUF

(SSPSR) for data transmission.

19.1.1.2

Enabling Master I/O

To enable the serial port, the SSPEN bit of the

SSPCON register, must be set. To reset or reconfigure

SPI mode, clear the SSPEN bit, re-initialize the

SSPCON register and then set the SSPEN bit. If a

Master mode of operation is selected in the SSPM bits

of the SSPCON register, the SDI, SDO and SCK pins

will be assigned as serial port pins.

For these pins to function as serial port pins, they must

have their corresponding data direction bits set or

cleared in the associated TRIS register as follows:

• SDI configured as input

• SDO configured as output

• SCK configured as output

Read

Write

Internal

Data Bus

SDI

SDO

RA5/SS

SCK

SSPSR Reg

SSPBUF Reg

SSPM<3:0>

bit 0

Shift

Clock

Control

Enable

Edge

Select

Clock Select

TMR2

FOSC

Prescaler

4, 16, 64

TRISx

RA0/SS

SSSEL

Output

2

Edge

Select

bit 7

Note:

The SSPSR is not directly readable or

writable and can only be accessed by

addressing the SSPBUF register.

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