PIC16F707-ESLASHML datasheet(159/284 Pages) MICROCHIP

159 / 284 page

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 159

PIC16F707/PIC16LF707

19.1.1.3

Master Mode Setup

In Master mode, the data is transmitted/received as

soon as the SSPBUF register is loaded with a byte

value. If the master is only going to receive, SDO output

could be disabled (programmed and used as an input).

The SSPSR register will continue to shift in the signal

present on the SDI pin at the programmed clock rate.

When initializing SPI Master mode operation, several

options need to be specified. This is accomplished by

programming the appropriate control bits in the

SSPCON and SSPSTAT registers. These control bits

allow the following to be specified:

• SCK as clock output

• Idle state of SCK (CKP bit)

• Data input sample phase (SMP bit)

• Output data on rising/falling edge of SCK (CKE bit)

• Clock bit rate

In Master mode, the SPI clock rate (bit rate) is user

selectable to be one of the following:

•FOSC/4 (or TCY)

•FOSC/16 (or 4

 TCY)

•FOSC/64 (or 16

 TCY)

• (Timer2 output)/2

This allows a maximum data rate of 5 Mbps

(at FOSC =20 MHz).

Figure 19-3 shows the waveforms for Master mode.

The clock polarity is selected by appropriately program-

ming the CKP bit of the SSPCON register. When the

CKE bit is set, the SDO data is valid before there is a

clock edge on SCK. The sample time of the input data

is shown based on the state of the SMP bit and can

occur at the middle or end of the data output time. The

time when the SSPBUF is loaded with the received

data is shown.

19.1.1.4

Sleep in Master Mode

In Master mode, all module clocks are halted and the

transmission/reception will remain in their current state,

paused, until the device wakes from Sleep. After the

device wakes up from Sleep, the module will continue

to transmit/receive data.

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