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PIC16F722-E/ML Datasheet(PDF) 225 Page - Microchip Technology |
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PIC16F722-E/ML Datasheet(HTML) 225 Page - Microchip Technology |
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225 / 302 page ![]() © 2009 Microchip Technology Inc. DS41341E-page 225 PIC16F72X/PIC16LF72X TABLE 23-2: OSCILLATOR PARAMETERS FIGURE 23-7: CLKOUT AND I/O TIMING Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym. Characteristic Freq. Tolerance Min. Typ† Max. Units Conditions OS08 HFOSC Internal Calibrated HFINTOSC Frequency(2) ±2% — 16.0 — MHz 0°C ≤ TA ≤ +85°C, VDD ≥ 2.5V ±5% — 16.0 — MHz -40°C ≤ TA ≤ +125°C OS08A MFOSC Internal Calibrated MFINTOSC Frequency(2) ±2% — 500 — kHz 0°C ≤ TA ≤ +85°C VDD ≥ 2.5V ±5% — 500 10 kHz -40°C ≤ TA ≤ +125°C OS10* TIOSC ST HFINTOSC Wake-up from Sleep Start-up Time —— 5 8 μs MFINTOSC Wake-up from Sleep Start-up Time — — 20 30 μs * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended. 3: By design. FOSC CLKOUT I/O pin (Input) I/O pin (Output) Q4 Q1 Q2 Q3 OS11 OS19 OS13 OS15 OS18, OS19 OS20 OS21 OS17 OS16 OS14 OS12 OS18 Old Value New Value Write Fetch Read Execute Cycle |
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