PIC16F722-ESLASHML datasheet(37/302 Pages) MICROCHIP

37 / 302 page

DS41341E-page 37

PIC16F72X/PIC16LF72X

3.5

Brown-Out Reset (BOR)

Brown-out Reset is enabled by programming the

BOREN<1:0> bits in the Configuration register. The

brown-out trip point is selectable from two trip points

via the BORV bit in the Configuration register.

Between the POR and BOR, complete voltage range

coverage for execution protection can be imple-

mented.

Two bits are used to enable the BOR. When

BOREN = 11, the BOR is always enabled. When

BOREN = 10, the BOR is enabled, but disabled during

Sleep. When BOREN = 0X, the BOR is disabled.

If VDD falls below VBOR for greater than parameter

(TBOR) (see Section 23.0 “Electrical Specifica-

tions”), the Brown-out situation will reset the device.

This will occur regardless of VDD slew rate. A Reset is

not ensured to occur if VDD falls below VBOR for more

than parameter (TBOR).

If VDD drops below VBOR while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Power-up Timer will be re-initialized. Once VDD

rises above VBOR, the Power-up Timer will execute a

64 ms Reset.

FIGURE 3-3:

BROWN-OUT SITUATIONS

Note:

When erasing Flash program memory, the

BOR is forced to enabled at the minimum

BOR setting to guarantee that any code

protection circuitry is operating properly.

64 ms(1)

VBOR

VDD

Internal

Reset

VBOR

VDD

Internal

Reset

64 ms(1)

< 64 ms

64 ms(1)

VBOR

VDD

Internal

Reset

Note 1:

64 ms delay only if PWRTE bit is programmed to ‘0’.

PIC16F722-E/ML Datasheet(PDF) 37 Page - Microchip Technology

PIC16F722-E/ML Datasheet(HTML) 37 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL