PIC16F722-ESLASHML datasheet(53/302 Pages) MICROCHIP

53 / 302 page

DS41341E-page 53

PIC16F72X/PIC16LF72X

6.0

I/O PORTS

There are as many as thirty-five general purpose I/O

pins available. Depending on which peripherals are

enabled, some or all of the pins may not be available as

general purpose I/O. In general, when a peripheral is

enabled, the associated pin may not be used as a

general purpose I/O pin.

6.1

Alternate Pin Function

The Alternate Pin Function Control (APFCON) register

is used to steer specific peripheral input and output

functions between different pins. The APFCON register

is shown in Register 6-1. For this device family, the

following functions can be moved between different

pins.

•SS (Slave Select)

• CCP2

APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER

U-0

R/W-0

—

SSSEL

CCP2SEL

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-2

Unimplemented: Read as ‘0’.

bit 1

SSSEL: SS Input Pin Selection bit

=SS function is on RA5/AN4/CPS7/SS/VCAP

=SS function is on RA0/AN0/SS/VCAP

bit 0

CCP2SEL: CCP2 Input/Output Pin Selection bit

= CCP2 function is on RC1/T1OSI/CCP2

= CCP2 function is on RB3/CCP2

PIC16F722-E/ML Datasheet(PDF) 53 Page - Microchip Technology

PIC16F722-E/ML Datasheet(HTML) 53 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL