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PIC16F722-E/ML Datasheet(PDF) 180 Page - Microchip Technology |
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PIC16F722-E/ML Datasheet(HTML) 180 Page - Microchip Technology |
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180 / 302 page ![]() PIC16F72X/PIC16LF72X DS41341E-page 180 © 2009 Microchip Technology Inc. 17.2.5 RECEPTION When the R/W bit of the received address byte is clear, the master will write data to the slave. If an address match occurs, the received address is loaded into the SSPBUF register. An address byte overflow will occur if that loaded address is not read from the SSPBUF before the next complete byte is received. An SSP interrupt is generated for each data transfer byte. The BF, R/W and D/A bits of the SSPSTAT register are used to determine the status of the last received byte. FIGURE 17-10: I2C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) P 9 8 7 6 5 D0 D1 D2 D3 D4 D5 D6 D7 S A7 A6 A5 A4 A3 A2 A1 SDA SCL 1 2 34 5 6 7 8 91 2 3 4 56 7 89 12 34 Bus Master sends Stop condition Bit SSPOV is set because the SSPBUF register is still full. Cleared in software SSPBUF register is read ACK Receiving Data Receiving Data D0 D1 D2 D3 D4 D5 D6 D7 ACK R/W = 0 Receiving Address SSPIF BF SSPOV ACK ACK is not sent. |
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