HCS12 datasheet(355/452 Pages) FREESCALE

355 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

355

9.5.1.2 Interrupt Details

The REV instruction includes a 3-cycle processing loop for each byte in the

rule list (including antecedents, consequents, and special separator

characters). Within this loop, a check is performed to see if any qualified

interrupt request is pending. If an interrupt is detected, the current CPU

registers are stacked and the interrupt is honored. When the interrupt

service routine finishes, an RTI instruction causes the CPU to recover its

previous context from the stack, and the REV instruction is resumed as if it

had not been interrupted.

The stacked value of the program counter (PC), in case of an interrupted

REV instruction, points to the REV instruction rather than the instruction that

follows. This causes the CPU to try to execute a new REV instruction upon

return from the interrupt. Since the CPU registers (including the V bit in the

condition codes register) indicate the current status of the interrupted REV

instruction, this effectively causes the rule evaluation operation to resume

from where it left off.

9.5.1.3 Cycle-by-Cycle Details for REV

The central element of the REV instruction is a 3-cycle loop that is executed

once for each byte in the rule list. There is a small amount of housekeeping

activity to get this loop started as REV begins and a small sequence to end

the instruction. If an interrupt comes, there is a special small sequence to

save CPU status on the stack before honoring the requested interrupt.

Figure 9-9 is a REV instruction flow diagram. Each rectangular box

represents one CPU clock cycle. Decision blocks and connecting arrows

are considered to take no time at all. The letters in the small rectangles in

the upper left corner of each bold box correspond to execution cycle codes

(refer to Section 6. Instruction Glossary for details). Lower case letters

indicate a cycle where 8-bit or no data is transferred. Upper case letters

indicate cycles where 16-bit or no data is transferred.

When a value is read from memory, it cannot be used by the CPU until the

second cycle after the read takes place. This is due to access and

propagation delays.

HCS12 Datasheet(PDF) 355 Page - Freescale Semiconductor, Inc