HCS12 datasheet(416/452 Pages) FREESCALE

416 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

416

Freescale Semiconductor

The IDIVS instruction is included specifically for C compilers, where

word-sized operands are divided to produce a word-sized result (unlike the

÷ 16 = 16 EDIV). The EMUL and EMULS instructions place the result in

registers so a C compiler can choose to use only 16 bits of the 32-bit result.

B.7.3 Code Size Reduction

CPU12 assembly language programs written from scratch tend to be

30 percent smaller than equivalent programs written for the M68HC11. This

figure has been independently qualified by Freescale programmers and an

independent C compiler vendor. The major contributors to the reduction

appear to be improved indexed addressing and the universal

transfer/exchange instruction.

In some specialized areas, the reduction is much greater. A fuzzy logic

inference kernel requires about 250 bytes in the M68HC11, and the same

program for the CPU12 requires about 50 bytes. The CPU12 fuzzy logic

Table B-3. Comparison of Math Instruction Speeds

Instruction

Mnemonic

Math

Operation

M68HC11

1 Cycle = 250 ns

M68HC11

With Coprocessor

1 Cycle = 250 ns

CPU12

1 Cycle = 40 ns

(125 ns in M68HC12)

MUL

× 8 = 16

(signed)

10 cycles

—

3 cycles

EMUL

× 16 = 32

(unsigned)

—

20 cycles

3 cycles

EMULS

× 16 = 32

(signed)

—

20 cycles

3 cycles

IDIV

÷ 16 = 16

(unsigned)

41 cycles

—

12 cycles

FDIV

÷ 16 = 16

(fractional)

41 cycles

—

12 cycles

EDIV

÷ 16 = 16

(unsigned)

—

33 cycles

11 cycles

EDIVS

÷ 16 = 16

(signed)

—

37 cycles

12 cycles

IDIVS

÷ 16 = 16

(signed)

—

12 cycles

EMACS

× (16 × 16) ⇒ 32

(signed MAC)

—

20 cycles

12 cycles

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