HCS12 datasheet(420/452 Pages) FREESCALE

420 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

420

Freescale Semiconductor

B.8.1 Memory-to-Memory Moves

The CPU12 has both 8- and 16-bit variations of memory-to-memory move

instructions. The source address can be specified with immediate,

extended, or indexed addressing modes. The destination address can be

specified by extended or indexed addressing mode. The indexed

addressing mode for move instructions is limited to modes that require no

extension bytes (9- and 16-bit constant offsets are not allowed), and indirect

indexing is not allowed for moves. This leaves 5-bit signed constant offsets,

accumulator offsets, and the automatic increment/decrement modes. The

following simple loop is a block move routine capable of moving up to 256

words of information from one memory area to another.

LOOP

MOVW

2,X+ , 2,Y+

;move a word and update pointers

DBNE

B,LOOP

;repeat B times

The move immediate to extended is a convenient way to initialize a register

without using an accumulator or affecting condition codes.

B.8.2 Universal Transfer and Exchange

The M68HC11 has only eight transfer instructions and two exchange

instructions. The CPU12 has a universal transfer/exchange instruction that

can be used to transfer or exchange data between any two CPU registers.

The operation is obvious when the two registers are the same size, but

some of the other combinations provide very useful results. For example

when an 8-bit register is transferred to a 16-bit register, a sign-extend

operation is performed. Other combinations can be used to perform a

zero-extend operation.

These instructions are used often in CPU12 assembly language programs.

Transfers can be used to make extra copies of data in another register, and

exchanges can be used to temporarily save data during a call to a routine

that expects data in a specific register. This is sometimes faster and

produces more compact object code than saving data to memory with

pushes or stores.

B.8.3 Loop Construct

The CPU12 instruction set includes a new family of six loop primitive

instructions. These instructions decrement, increment, or test a loop count

in a CPU register and then branch based on a zero or non-zero test result.

The CPU registers that can be used for the loop count are A, B, D, X, Y, or

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