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SA9101 Datasheet(PDF) 27 Page - Sames |
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SA9101 Datasheet(HTML) 27 Page - Sames |
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27 / 40 page ![]() SA9101 sames 27/40 ADR 1 Extended Mode Register 1 Register Bit Description Name CX1B0 0 Enable Double Frame marker 0: Normal 1: Marker enabled and provided at CHPAR pin. CX1B1 1 Not used CX1B2 2 Fully Bauded data format 0: Half bauded 1: Fully bauded CX1B3 3 Extended Code Violation Counter mode CX1B4 4 S i-bit zero counter enable CX1B5 5 Receive Transparent Mode CX1B6 6 Time slot 0 Extended Signalling Transparent Mode. If set, in Double frame and CRC Multiframe formats only the S n bits are transmitted as applied at DXI CX1B7 7 Not used ADR 6 - 9 Idle Channel Register Bank CX6 IC0 IC1 IC2 IC3 IC4 IC5 IC6 IC7 CX7 IC8 IC15 CX8 IC16 IC23 CX9 IC24 IC31 0: Normal operation, 1: Idle Channel mode Note: Timeslot 0 information is overwritten by idle channel code according to the transparency mode selected. If Timeslot 16 Signalling stack is enabled and Timeslot 16 is selected for Idle Channel Code, the idle channel selection will be ignored. The stack has higher priority. |
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