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KM416RD8ACD-RK70 Datasheet(PDF) 21 Page - Samsung semiconductor

Part # KM416RD8ACD-RK70
Description  128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
PDF  64 Pages
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

KM416RD8ACD-RK70 Datasheet(HTML) 21 Page - Samsung semiconductor

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Page 18
KM416RD8AC(D)/KM418RD8AC(D)
Direct RDRAM
Rev. 1.01 Oct. 1999
Precharge Mechanisms
Figure 13 shows an example of precharge with the ROWR
packet mechanism. The PRER command must occur a time
tRAS after the ACT command, and a time tRP before the next
ACT command. This timing will serve as a baseline against
which the other precharge mechanisms can be compared.
Figure 14 (top) shows an example of precharge with a RDA
command. A bank is activated with an ROWA packet on the
ROW pins. Then, a series of four dualocts are read with RD
commands in COLC packets on the COL pins. The fourth of
these commands is a RDA, which causes the bank to auto-
matically precharge when the final read has finished. The
timing of this automatic precharge is equivalent to a PRER
command in an ROWR packet on the ROW pins that is
offset a time tOFFP from the COLC packet with the RDA
command. The RDA command should be treated as a RD
command in a COLC packet as well as a simultaneous (but
offset) PRER command in an ROWR packet when analyzing
interactions with other packets.
Figure 14 (middle) shows an example of precharge with a
WRA command. As in the RDA example, a bank is acti-
vated with an ROWA packet on the ROW pins. Then, two
dualocts are written with WR commands in COLC packets
on the COL pins. The second of these commands is a WRA,
which causes the bank to automatically precharge when the
final write has been retired. The timing of this automatic
precharge is equivalent to a PRER command in an ROWR
packet on the ROW pins that is offset a time tOFFP from the
COLC packet that causes the automatic retire. The WRA
command should be treated as a WR command in a COLC
packet as well as a simultaneous (but offset) PRER
command in an ROWR packet when analyzing interactions
with other packets. Note that the automatic retire is triggered
by a COLC packet a time tRTR after the COLC packet with
the WR command unless the second COLC contains a RD
command to the same device. This is described in more
detail in Figure 17.
Figure 14 (bottom) shows an example of precharge with a
PREX command in an COLX packet. A bank is activated
with an ROWA packet on the ROW pins. Then, a series of
four dualocts are read with RD commands in COLC packets
on the COL pins. The fourth of these COLC packets
includes an COLX packet with a PREX command. This
causes the bank to precharge with timing equivalent to a
PRER command in an ROWR packet on the ROW pins that
is offset a time tOFFP from the COLX packet with the PREX
command.
Figure 13: Precharge via PRER Command in ROWR Packet
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T0
T4
T8
T12
T1
T5
T9
T13
T2
T6
T10
T14
T3
T7
T11
T15 T16
T20
T24
T28
T17
T21
T25
T29
T18
T22
T26
T30
T19
T23
T27
T31 T32
T36
T40
T44
T33
T37
T41
T45
T34
T38
T42
T46
T35
T39
T43
T47
ACT a0
PRER a5
tRAS
tRC
a0 = {Da,Ba,Ra}
a5 = {Da,Ba}
b0 = {Da,Ba,Rb}
tRP
ACT b0



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