PIC18F23K22-ESLASHML datasheet(323/496 Pages) MICROCHIP

323 / 496 page

 2010 Microchip Technology Inc.

Preliminary

DS41412C-page 323

PIC18(L)F2X/4XK22

19.3.2

CAPACITANCE CALIBRATION

There is a small amount of capacitance from the

internal A/D Converter sample capacitor as well as

stray capacitance from the circuit board traces and

pads that affect the precision of capacitance

measurements.

measurement

the

stray

capacitance can be taken by making sure the desired

capacitance to be measured has been removed. The

measurement is then performed using the following

steps:

Initialize the A/D Converter and the CTMU.

Set EDG1STAT (= 1).

Wait for a fixed delay of time t.

Clear EDG1STAT.

Perform an A/D conversion.

Calculate the stray and A/D sample capacitances:

where I is known from the current source measurement

step, t is a fixed delay and V is measured by performing

an A/D conversion.

This measured value is then stored and used for

calculations of time measurement or subtracted for

capacitance measurement. For calibration, it is

expected that the capacitance of CSTRAY + CAD is

approximately known. CAD is approximately 4 pF.

An iterative process may need to be used to adjust the

time, t, that the circuit is charged to obtain a reasonable

voltage reading from the A/D Converter. The value of t

may be determined by setting COFFSET to a theoretical

value, then solving for t. For example, if CSTRAY is

theoretically calculated to be 11 pF, and V is expected

to be 70% of VDD, or 2.31V, then t would be:

or 63

s.

See Example 19-3 for a typical routine for CTMU

capacitance calibration.

COFFSET

CSTRAY CAD



 V



(4 pF + 11 pF) • 2.31V/0.55

A

PIC18F23K22-E/ML Datasheet(PDF) 323 Page - Microchip Technology

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