C5NPD0-DS datasheet(43/100 Pages) FREESCALE

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Pin Descriptions Grouped by Function

V 04

7 SPLD is asserted for one SPCLK cycle, loading the first PROM_DATA into the network

processor PROM_RETURN_DATA register and the second PROM_DATA into the

external shift register.

8 SPLD is deasserted for 22 SPCLK cycles, shifting the second PROM_DATA into the

network processor internal shift register.

9 SPLD is asserted for one SPCLK cycle, loading the second PROM_DATA into the

network processor PROM_RETURN_DATA register.

Figure 5 PROM Interface Timing Outline

General System Interface Signal

Table 17 provides the signal for the Executive Processor reset power status and I/O clock.

The C-5 NP can be powered up with the XP either running or with the XP in reset mode

similar to the CPs. When the XP remains in reset mode, an external host can be used to

control the initialization of the C-5 NP.

SPCLK

SPLD

678

12 13 14 15 16 17 18 19 20 21 22 23 12

567

10 11 12 13 14 15 16 17 18 19 20 21 22 23 1

10 11 12 13 14 15 16 17 18

21 22 23 1

SPDTO

The PROM_ADDR is loaded into the

C-5’s internal shift register.

The PROM_ADDR is shifted into

the external shift register.

(SPCLK Rising Edge used for shifting)

The PROM_ADDR is loaded into the

external presentation register.

The PROM_DATA is

presenting.

The PROM_DATA is loaded into the

external shift register.

The PROM_DATA is shifted into the C-5’s

Internal shift register.

The PROM_DATA is loaded into the C-5’s

internal PROM_RETURN_DATA register.

SPDTI

xxxx

XP PROM Interface outline

XP PROM Interface detail

SPLD

SPDTO

SPDTI

‘

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C5NPD0-DS Datasheet(PDF) 43 Page - Freescale Semiconductor, Inc

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