C5NPD0-DS datasheet(47/100 Pages) FREESCALE

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Pin Descriptions Grouped by Function

V 04

BMU SDRAM Interface

Signals

The BMU and SDRAM interface signals are described in Table 23.

The BMU is designed to support SDRAM devices with 12 address lines. All 139 data lines

and all 12 address lines must be connected to the SDRAM in order for the BMU to be able

to read and write external SDRAM properly.

Table 22 Power X Mode, C-5 Network Processor to Fabric Interface Pin Mapping

RECEIVE SIGNALS

TRANSMIT SIGNALS

C-5 NETWORK

PROCESSOR

I/O

POWER X

NOTE

C-5 NETWORK

PROCESSOR

I/O

POWER X

NOTE

FRXCTL0

Input

RxCtrl[0]

Pulldown

FTXCTL0

Output

TxCtrl[0]

Pulldown or nc

FRXCTL1

Input

RxCtrl[1]

Pulldown

FTXCTL1

Output

TxCtrl[1]

Pulldown or nc

FRXCTL2

Input

RxCtrl[2]

Pulldown

FTXCTL2

Output

TxCtrl[2]

Pulldown or nc

FRXCTL3

Input

RxPrty[3]

FTXCTL3

Output

TxPrty[3]

FRXCTL4

Input

RxPrty[2]

FTXCTL4

Output

TxPrty[2]

FRXCTL5

Input

RxPrty[1]

FTXCTL5

Output

TxPrty[1]

FRXCTL6

Input

RxPrty[0]

FTXCTL6

Output

TxPrty[0]

Table 23 BMU SDRAM Interface Signals

SIGNAL NAME

PIN #

TOTAL

TYPE

I/O

SIGNAL DESCRIPTION

MD0 - MD129

R29, Q28, P28, S28, R28, P29, R27,

Q26, P26, S26, R26, P27, R25, Q24,

P24, S24, R24, P25, S22, R23, R22,

N29, M28, L28, J29, O28, N28, L29,

K28, N27, M26, L26, J28, O26, N26,

L27, K26, N25, M24, L24, J27, O24,

N24, L25, K24, P22, M22, K22, J23,

Q22, N23, L22, J25, O22, L23, J26,

J22, P23, N22, L21, J24, B29, D29,

F29, A28, C28, E28, G28, B28, D28,

F28, B27, D27, F27, A26, C26, E26,

B26, D26, F26, G26, B25, D25, F25,

A24, C24, E24, B24, D24, F24, B23,

D23, F23, G24, A22, C22, E22, B22,

D22, F22, B21, D21, F21, A20, C20,

E20, G22, B20, D20, F20, B19, D19,

F19, A18, C18, E18, B18, D18, F18,

G20, B17, D17, F17, A16, C16, E16,

B16, D16, F16, B15

130

LVTTL

I/O

Data Lines In

MDECC0 - MDECC8 G16, F15, F14, E14, D15, D14, C14,

B14, A14

LVTTL

I/O

Stored as data, ECC bits

Freescale Semiconductor, Inc.

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