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ST10F276Z5 Datasheet(PDF) 200 Page - STMicroelectronics

Part # ST10F276Z5
Description  16-bit MCU with MAC unit, 832 Kbyte Flash memory and 68 Kbyte RAM
PDF  239 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F276Z5 Datasheet(HTML) 200 Page - STMicroelectronics

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Electrical characteristics
ST10F276Z5
200/239
Due to this adaptation to the input clock, the frequency of fCPU is constantly adjusted so it is
locked to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of
individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated
using the minimum TCL that is possible under the respective circumstances.
The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes fCPU to
keep it locked on fXTAL. The relative deviation of TCL is the maximum when it is referred to
one TCL period.
This is especially important for bus cycles using wait states and e.g. for the operation of timers,
serial interfaces, etc. For all slower operations and longer periods (such as, for example, pulse
train generation or measurement, lower baud rates) the deviation caused by the PLL jitter is
negligible. Refer to next Section 23.8.9: PLL Jitter for more details.
23.8.8
Voltage controlled oscillator
The ST10F276Z5 implements a PLL which combines different levels of frequency dividers
with a Voltage Controlled Oscillator (VCO) working as frequency multiplier. The following
table presents a detailed summary of the internal settings and VCO frequency.
The PLL input frequency range is limited to 1 to 3.5 MHz, while the VCO oscillation range is
64 to 128 MHz. The CPU clock frequency range when PLL is used is 16 to 64 MHz.
Example 1
●
FXTAL = 10 MHz
●
P0(15:13) = ‘110’ (multiplication by 3)
●
PLL input frequency = 2.5 MHz
●
VCO frequency = 120 MHz
●
PLL output frequency = 30 MHz
(VCO frequency divided by 4)
●
FCPU = 30 MHz (no effect of output prescaler)
Table 98.
Internal PLL divider mechanism
P0.15-13
(P0H.7-5)
XTAL
frequency
Input
prescaler
PLL
Output
prescaler
CPU frequency
fCPU = fXTAL x F
Multiply by
Divide by
11
14 to 8 MHz
FXTAL / 4
64
4
–
FXTAL x 4
11
0
5.3 to
10.6 MHz
FXTAL / 4
48
4
–
FXTAL x 3
10
14 to 8 MHz
FXTAL / 4
64
2
–
FXTAL x 8
10
06.4 to 12 MHz FXTAL / 4
40
2
–
FXTAL x 5
01
11 to 64 MHz
–
PLL bypassed
–
FXTAL x 1
01
04 to 6.4 MHz
FXTAL / 2
40
2
–
FXTAL x 10
0
0
1
4 to 12 MHz
–
PLL bypassed
FPLL / 2
FXTAL / 2
00
04 MHz
FXTAL / 2
64
2
–
FXTAL x 16



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