forming a digital representation of the analog input sig-

nal. During the conversion period, the MAX1069 holds

SCL low (clock stretching).

The time required for the T/H to acquire an input signal

is a function of the analog input source impedance. If

the input signal source impedance is high, lengthen the

hold capacitance must acquire a charge representing

the input signal. Minimize the input source impedance

less than 12.9k

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

12

______________________________________________________________________________________

Figure 3. MAX1069 Simplified Functional Diagram

AIN

AGNDS

CONTROL

LOGIC

4MHz

INTERNAL

OSCILLATOR

OUTPUT SHIFT

REGISTER

T/H

SAR

ADC

REF

CLOCK

IN

OUT

+4.096V

REFERENCE

REFADJ

REF

5k

Ω

ADD0

ADD1

ADD2

ADD3

DVDD

AVDD

DGND

SCL

SDA

AGND

8

13

12

11

9

1

2

3

4

5

6

7

10

14

MAX1069

Figure 4. Typical Application Circuit

AIN

REF

10

µF

0.1

µF

REFADJ

AGNDS

AVDD

0.1

µF

AGND

DGND

ANALOG

SOURCE

ADD1

ADD0

ADD2

SCL

SDA

DVDD

0.1

µF

3.0V

5.0V

µC

SDA

SCL

ADD3

8

13

12

11

14

91

2

3

4

5

6

7

10

MAX1069