of a STOP condition to leave the bus active and in its

current timing mode (see the

HS-Mode section).

Acknowledge Bits

Successful data transfers are acknowledged with an

acknowledge bit (A) or a not-acknowledge bit (A). Both

the master and the MAX1069 (slave) generate acknowl-

edge bits. To generate an acknowledge, the receiving

device must pull SDA low before the rising edge of the

acknowledge-related clock pulse (ninth pulse) and

keep it low during the high period of the clock pulse

(Figure 8). To generate a not acknowledge, the receiver

allows SDA to be pulled high before the rising edge of

the acknowledge-related clock pulse and leaves it high

during the high period of the clock pulse.

Monitoring the acknowledge bits allows for detection of

unsuccessful data transfers. An unsuccessful data

transfer happens if a receiving device is busy or if a

system fault has occurred. In the event of an unsuc-

cessful data transfer, the master should reattempt com-

munication at a later time.

Slave Address

A master initiates communication with a slave device by

issuing a START condition followed by a slave address

byte. As shown in Figure 9, the slave address byte con-

sists of 7 address bits and a read/write bit (R/W). When

idle, the MAX1069 continuously waits for a START con-

dition followed by its slave address. When the

MAX1069 recognizes its slave address, it acquires the

analog input signal and prepares for conversion. The

first three bits (MSBs) of the slave address have been

factory programmed and are always 011. Connecting

ADD3–ADD0 to DVDD or DGND, programs the last four

bits (LSBs) of the slave address high or low.

Since the MAX1069 does not require setup or configu-

ration, the least significant bit (LSB) of the address byte

(R/W) controls power-down. In external reference mode

ence mode, setting R/W = 1 places the device in nor-

mal operation and setting R/W = 0 powers down the

internal reference following the conversion (see the

Internal Reference Shutdown section).

After receiving the address, the MAX1069 (slave)

issues an acknowledge by pulling SDA low for one

clock cycle.

Bus Timing

At power-up, the MAX1069 bus timing defaults to fast

mode (F/S-mode), allowing conversion rates up to

19ksps. The MAX1069 must operate in high-speed

mode (HS-mode) to achieve conversion rates up to

58.6ksps. Figure 1 shows the bus timing for the

MAX1069 2-wire interface.

HS-Mode

At power-up, the MAX1069 bus timing is set for F/S-

mode. The master selects HS-mode by addressing all

devices on the bus with the HS-mode master code 0000

1XXX (X = don’t care). After successfully receiving the

HS-mode master code, the MAX1069 issues a not

acknowledge allowing SDA to be pulled high for one

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

14

______________________________________________________________________________________

Figure 8. Acknowledge Bits

12

8

9

ACKNOWLEDGE

NOT ACKNOWLEDGE

SCL

S

SDA

Figure 7. START and STOP Conditions

SP

Sr

SCL

SDA