MAX1069 datasheet(6/20 Pages) MAXIM

6 / 20 page

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

_______________________________________________________________________________________

Note 9: A master device must provide a data hold time for SDA (referred to VIL of SCL) in order to bridge the undefined region of

SCL’s falling edge (see Figure 1).

Note 10: CB = total capacitance of one bus line in pF. tR and tF measured between 0.3 VDVDD and 0.7 VDVDD.

Note 11: fSCL must meet the minimum clock low time plus the rise/fall times.

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD = +4.75V to +5.25V, VDVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external

reference applied to REF, REFADJ = AVDD, CREF = 10µF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

Figure 1. I2C Serial Interface Timing

tHD,STA

tHIGH

tRCL

tFCL

tHD,STA

SCL

SDA

tSU,STA

tSU,STO

tRCL1

tBUF

tLOW

tSU,DAT

tHD,DAT

tSU,DAT

tHD,STA

SCL

SDA

tSU,STA

tLOW

HS-MODE

F/S-MODE

A. F/S-MODE I2C SERIAL INTERFACE TIMING

B. HS-MODE I2C SERIAL INTERFACE TIMING

tRDA

tFDA

PARAMETERS ARE MEASURED FROM 30% TO 70%.

Figure 2. Load Circuit

VOUT

VDD

IOL = 3mA

IOH = 0mA

400pF

DIGITAL

I/O

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