after a conversion. This allows more time for the input

buffer amplifier to respond to a large step-change in

input signal. The input amplifier must have a high

enough slew rate to complete the required output volt-

age change before the beginning of the acquisition

time. At the beginning of acquisition, the internal sam-

pling capacitor array connects to AIN (the amplifier out-

put), causing some output disturbance.

Ensure that the sampled voltage has settled to within

the required limits before the end of the acquisition

time. If the frequency of interest is low, AIN can be

bypassed with a large enough capacitor to charge the

internal sampling capacitor with very little ripple.

However, for AC use, AIN must be driven by a wide-

band buffer (at least 4MHz), which must be stable with

the ADC’s capacitive load (in parallel with any AIN

bypass capacitor used) and also settle quickly. Refer to

Maxim’s website at www.maxim-ic.com for application

notes on how to choose the optimum buffer amplifier for

your ADC application.

Layout, Grounding, and Bypassing

Careful printed circuit (PC) layout is essential for the

best system performance. Boards should have sepa-

rate analog and digital ground planes and ensure that

digital and analog signals are separated from each

other. Do not run analog and digital (especially clock)

lines parallel to one another, or digital lines underneath

the device package.

Figure 4 shows the recommended system ground con-

nections. Establish an analog ground point at AGND

and a digital ground point at DGND. Connect all analog

grounds to the star analog ground. Connect the digital

grounds to the star digital ground. Connect the digital

ground plane to the analog ground plane at one point.

For lowest-noise operation, make the ground return to

the star ground’s power-supply low impedance and

make it as short as possible.

High-frequency noise in the AVDD power supply

degrades the ADC’s high-speed comparator perfor-

mance. Bypass AVDD to AGND with a 0.1µF ceramic

surface-mount capacitor. Make bypass capacitor con-

nections as short as possible. If the power supply is

very noisy, connect a 10

Ω resistor in series with AVDD

and a 4.7µF capacitor from AVDD to AGND to create a

lowpass RC filter.

Definitions

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values

on an actual transfer function from a straight line. This

straight line can be either a best-straight-line fit or a line

drawn between the end points of the transfer function

once offset and gain errors have been nullified. The

MAX1069 INL is measured using the endpoint method.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between

an actual step width and the ideal value of 1LSB. A

DNL error specification of less than 1LSB guarantees

no missing codes and a monotonic transfer function.

Aperture Jitter

the time between the samples (Figure 11).

Aperture Delay

SCL to the instant when an actual sample is taken

(Figure 11).

Signal-to-Noise Ratio

For a waveform perfectly reconstructed from digital sam-

ples, signal-to-noise ratio (SNR) is the ratio of full-scale

analog input (RMS value) to the RMS quantization error

(residual error). The ideal, theoretical minimum analog-

to-digital noise is caused by quantization error only and

results directly from the ADC’s resolution (N bits):

In reality, noise sources besides quantization noise

exist, including thermal noise, reference noise, clock jit-

ter, etc. Therefore, SNR is computed by taking the ratio

of the RMS signal to the RMS noise, which includes all

spectral components minus the fundamental, the first

five harmonics, and the DC offset.

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

18

______________________________________________________________________________________

Figure 14. Unipolar Transfer Function

AGNDS

INPUT VOLTAGE (LSB)

01 2 3

16384

1LSB =

16383

16381

0...000

0...001

0...010

0...011

1...111

1...110

1...101

1...100