IC-MLEVALML1D datasheet(13/17 Pages) ICHAUS

13 / 17 page

iC-ML

HALL Position Sensor / Encoder

Rev A3, Page 13/17

In the various chain modes multiple iC-MLs can be ar-

ranged in a chain (see Figure 14) where all of the de-

vices are connected by a shared CLK line (pin B). The

NEN input is evaluated synchronously with the rising

CLK edge. If the NEN input is switched to low, the

device is active during the following CLK cycle(s). To

allow the devices to be cascaded a delayed enable sig-

nal is generated at output pin NENO (pin D) with which

the follow-on device can be activated. If the NEN in-

put of the ﬁrst device in the chain is reset to high, all

devices in the chain are deactivated. Bus lines A (pin

A) and C (pin C) are activated by tristate output stages

which are high impedance when NEN is high and CLK

is low and also following the second rising CLK edge.

AB chain mode

In AB chain mode two A/B digital incremental signals

are generated at ports A and C. The two square-wave

signals are phase shifted at either +90° or -90°, de-

pending on the direction of rotation. Following a CLK

pulse the next device in the chain is enabled. Here the

falling CLK edge deactivates the current device (e.g.

ML 1 in Figure 14) and activates the next device in the

chain (ML 2) with a low signal at its NEN input. After

a device has been activated the two bus lines A (port

A) and B (port C) are ﬁrst switched to low (see Figure

15). This is then followed by the incremental signals

being output, starting at the zero position. In the event

of error the bus lines remain low.

D chain mode

In D chain mode differential sine and cosine signals

are generated at ports A and C. During the ﬁrst clock

pulse signals PSIN and PCOS are presented to the

bus; during the second pulse signals NSIN and NCOS

are on the bus (see Figure 15). In this mode each

device is thus active for two clock pulses. During the

ﬁrst clock pulse the non-inverted sine (port A) and co-

sine (port C) signals are ﬁrst presented to the bus, with

the inverted signals following on the positive CLK edge

during the second pulse. The falling CLK edge in the

second clock pulse deactivates the current device and

activates the following device in the chain with a low

signal at its NEN input.

S chain mode

In S chain mode the non-inverted sine (port A) and co-

sine (port C) signals are presented to the bus during

the ﬁrst clock pulse, with the signals VREF (port A)

and GAIN (port C) following on the positive CLK edge

of the next pulse. Each device is thus active for two

clock pulses. The falling CLK edge in the second clock

pulse deactivates the current device and activates the

following device in the chain with a low signal at its

NEN input.

The sine and cosine signals can be assessed using

signal VREF. Signal GAIN (pin D) indicates iC-ML’s in-

ternal ampliﬁcation (see Electrical Characteristics No.

207) and can be used to estimate the signal amplitude

of the internal Hall sensor. The GAIN signal can also

be used to adjust the rotary axis of the magnet to the

center of the chip.

100

200

300

400

500

600

700

Time [µs]

NEN

CLK

NENO

Figure 16: Bus signals and control signals in S

chain mode

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