MPC8358E datasheet(16/95 Pages) FREESCALE

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MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3

Freescale Semiconductor

RESET Initialization

5.2

RESET AC Electrical Characteristics

This section describes the AC electrical specifications for the reset initialization timing requirements of

the device. Table 10 provides the reset initialization AC timing specifications for the DDR SDRAM

component(s).

Output low voltage

VOL

IOL = 3.2 mA

—

0.4

Notes:

1. This table applies for pins PORESET, HRESET, SRESET, and QUIESCE.

2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins.

Table 10. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Notes

Required assertion time of HRESET or SRESET (input) to activate reset flow

—

tPCI_SYNC_IN

Required assertion time of PORESET with stable clock applied to CLKIN

when the device is in PCI host mode

—

tCLKIN

Required assertion time of PORESET with stable clock applied to

PCI_SYNC_IN when the device is in PCI agent mode

—

tPCI_SYNC_IN

HRESET/SRESET assertion (output)

512

—

tPCI_SYNC_IN

HRESET negation to SRESET negation (output)

—

tPCI_SYNC_IN

Input setup time for POR config signals (CFG_RESET_SOURCE[0:2] and

CFG_CLKIN_DIV) with respect to negation of PORESET when the device is

in PCI host mode

4—

tCLKIN

Input setup time for POR config signals (CFG_RESET_SOURCE[0:2] and

CFG_CLKIN_DIV) with respect to negation of PORESET when the device is

in PCI agent mode

4—

tPCI_SYNC_IN

Input hold time for POR config signals with respect to negation of HRESET

0—

Time for the device to turn off POR config signals with respect to the

assertion of HRESET

—4

Time for the device to turn on POR config signals with respect to the negation

of HRESET

1—

tPCI_SYNC_IN

1, 3

Notes:

1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary

clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the

MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual for more details.

2. tCLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode. See the

MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual for more details.

3. POR config signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.

Table 9. RESET Pins DC Electrical Characteristics (continued)

Characteristic

Symbol

Condition

Min

Max

Unit

MPC8358E Datasheet(PDF) 16 Page - Freescale Semiconductor, Inc

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