MPC8358E datasheet(17/95 Pages) FREESCALE

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MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3

Freescale Semiconductor

RESET Initialization

Table 11 provides the PLL and DLL lock times.

5.3

QUICC Engine Block Operating Frequency Limitations

This section specify the limits of the AC electrical characteristics for the operation of the QUICC Engine

block’s communication interfaces.

NOTE

The settings listed below are required for correct hardware interface

operation. Each protocol by itself requires a minimal QUICC Engine block

operating frequency setting for meeting the performance target. Because the

performance is a complex function of all the QUICC Engine block settings,

the user should make use of the QUICC Engine block performance utility

tool provided by Freescale to validate their system.

Table 12 lists the maximal QUICC Engine block I/O frequencies and the minimal QUICC Engine block

core frequency for each interface.

Table 11. PLL and DLL Lock Times

Parameter/Condition

Min

Max

Unit

Notes

PLL lock times

—

100

μs—

DLL lock times

7680

122,880

csb_clk cycles

1, 2

Notes:

1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio

results in the minimum and an 8:1 ratio results in the maximum.

2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 22, “Clocking,” for more information.

Table 12. QUICC Engine Block Operating Frequency Limitations

Interface

Interface Operating

Frequency (MHz)

Max Interface Bit

Rate (Mbps)

Min QUICC Engine

Operating

Frequency1 (MHz)

Notes

Ethernet Management: MDC/MDIO

10 (max)

—

MII

25 (typ)

100

—

RMII

50 (typ)

100

—

GMII/RGMII/TBI/RTBI

125 (typ)

1000

250

—

SPI (master/slave)

10 (max)

—

UCC through TDM

50 (max)

× F2

MCC

25 (max)

16.67

× F

2, 4

UTOPIA L2

50 (max)

800

× F2

POS-PHY L2

50 (max)

800

× F2

HDLC bus

10 (max)

—

HDLC/transparent

50 (max)

8/3

× F2, 3

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