MPC5602D Microcontroller Product Brief, Rev. 3.1

Preliminary—Subject to Change Without Notice

Device family overview

Freescale Semiconductor

8

•

Frequency modulated phase-locked loop

•

1. Assuming that the absolute maximum of 150 °C junction temperature is respected

NOTES:

APD: Analog power-down

BAM: Boot Assist Module Software and Hardware used for device startup and configuration

CG: Clock Gated, Powered but clock stopped

FP: VREG Full Performance mode

LP: VREG Low Power mode, reduced output capability of VREG but lower power consumption

Off: Powered off and clock gated

On: Powered and clocked

OP: Optionally configurable to be enabled or disabled (clock gated)

POR: Power-on reset

Var: Variable duration, based on the required reconfiguration and execution clock speed configuration

SOC features

Clock sources

This does not account for all durations at wakeup. Other delays will be necessary to consider including, but not

limited to the external supply startup time.

IRC wakeup time must not be added to the overall wakeup time as it starts in parallel with the VREG.

All other wakeup times must be added to determine the total startup time. For example, out of STANDBY, if Flash

is needed, the total wakeup time will be 120 µs.

RUN

On

OP

OP

On

OP On OP On —

— FP

—

—

—

—

—

—

—

HALT

CG

OP

OP

On

OP On OP On OP OP FP

—

—

—

—

—

STOP

CG

OP APD

On

CG OP OP On OP OP LP

25 µs 8 µs >125 µs 8 ms 200 µs — 33 µs

Off

Off

Off

Off OP Off OP OP OP LP

25 µs 8 µs >125 µs 8 ms 200 µs Var 33 µs

POR

—

—

—

—

—

—

—

—

—

—

— 250 µs 8 µs >125 µs 8 ms 200 µs —

BAM