MPC5602D Microcontroller Product Brief, Rev. 3.1

Preliminary—Subject to Change Without Notice

Device family overview

Freescale Semiconductor

10

3.3

Low power operation

MPC5602D devices provide two dynamic power modes—RUN and HALT—and two static low power

modes—STANDBY and STOP.

Both low power modes use clock gating to halt the clock for all or part of the device. Additionally, the

STANDBY mode uses power gating to automatically turn off the power supply to parts of the device to

minimize leakage.

RUN modes are the main operating modes where the entire device can be powered and clocked. Four

dynamic RUN modes are supported—RUN0 - RUN3. The ability to configure and select different RUN

modes enables different clocks and power configurations to be supported with respect to each other and to

allow switching between different operating conditions. The necessary peripherals, clock sources, clock

speed and systems clock prescalers can be independently configured for each of the four RUN modes of

the device.

HALT mode is a reduced activity, low power mode intended for moderate periods of lower processing

activity. In this mode the core system clocks are stopped but user-selected peripheral tasks can continue to

run. It can be configured to provide more efficient power management features (switch-off PLL, Flash

memory, main regulator, etc.) at the cost of longer wake up latency. The system returns to RUN mode as

soon as an event or interrupt is pending.

STOP mode maintains power to the entire device allowing the retention of all on-chip registers and

memory, and providing a faster recovery low power mode than the lowest STANDBY mode. There is no

need to reconfigure the device before executing code. The clocks to the core and peripherals are halted and

can be optionally stopped to the oscillator or PLL at the expense of a slower start-up time.

STOP is entered from RUN mode only. Wakeup from STOP mode is triggered by an external event or by

the internal periodic wakeup, if enabled.

NOTES:

in this table are only estimates and have not been validated.

Parameter

Reference frequency range

4 MHz – 16 MHz

CPU clock frequency range

0 Hz – 48 MHz

PLL multipliers

TBD

PLL dividers

TBD

PLL output frequency

16 – 48 MHz

Modulation depth

4%

Modulation frequency

TBD

PLL long term jitter

10 ns

<200 µs