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IMX53CEC Datasheet(PDF) 149 Page - Freescale Semiconductor, Inc |
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IMX53CEC Datasheet(HTML) 149 Page - Freescale Semiconductor, Inc |
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149 / 204 page  Boot Mode Configuration i.MX53xD Applications Processors for Consumer Products, Rev. 2 Freescale Semiconductor 149 5.3 Power setup during Boot By default, VDD_DIG_PLL is driven from internal on-die 1.2 V linear regulator (LDO). In order to achieve the standard operating mode (see VDD_DIG_PLL on Table 7), LDO output to VDD_DIG_PLL should be configured by software by boot code after power-up to 1.3 V output. This is done by programming the PLL1P2_VREG bits. EIM EIM EIM • Lower 16 bit data bus A/D multiplexed or upper 16 bit data bus non multiplexed • Only CS0 is supported. NAND Flash EXTMC NAND • 8/16 bit • NAND data can be muxed either over EIM data or PATA data • Only CS0 is supported SD/MMC eSDHCv2-1 PATA_DATA[11:8], SD1_DATA[3:0], SD1_CMD, SD1_CLK 1, 4 or 8 bit SD/MMC eSDHCv2-2 PATA_DATA[15:12], SD2_CLK, SD2_CMD, SD2_DATA[3:0] 1, 4 or 8 bit SD/MMC eSDHCv3-3 PATA_RESET_B, PATA_IORDY, PATA_DA_0, PATA_DATA[3:0], PATA_DATA[11:8] 1, 4 or 8 bit SD/MMC eSDHCv2-4 PATA_DA1, PATA_DA_2, PATA_DATA[7:4], PATA_DATA[15:12] 1, 4 or 8 bit I2C I2C-1 EIM_D21, EIM_D28 — I2C I2C-2 EIM_D16, EIM_EB2 — I2C I2C-3 EIM_D[18:17] — PATA PATA PATA_DIOW, PATA_DMACK, PATA_DMARQ, PATA_BUFFER_EN, PATA_INTRQ, PATA_DIOR, PATA_RESET_B, PATA_IORDY, PATA_DA_[2:0], PATA_CS_[1:0], PATA_DATA[15:0] — SATA SATA_PHY SATA_TXM, SATA_TXP, SATA_RXP, SATA_RXM, SATA_REXT, SATA_REFCLKM, SATA_REFCLKP — UART UARTv2-1 CSI0_DAT[11:10] RXD/TXD only UART UARTv2-2 PATA_DMARQ, PATA_BUFFER_EN RXD/TXD only UART UARTv2-3 EIM_D24, EIM_D25 RXD/TXD only UART UARTv2-4 CSI0_DAT[13:12] RXD/TXD only UART UARTv2-5 CSI0_DAT[15:14] RXD/TXD only USB USB-OTG PHY USB_H1_GPANAIO USB_H1_RREFEXT USB_H1_DP USB_H1_DN USB_H1_VBUS — Table 110. Interfaces Allocation During Boot (continued) Interface IP Instance Allocated Pads During Boot Comment |
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