FM3130-G datasheet(19/22 Pages) RAMTRON

19 / 22 page

ire

FM3130 Integrated RTC/Alarm with 64Kb FRAM

Rev. 3.2

Sept. 2011

Page 19 of 22

AC Test Conditions

Equivalent AC Test Load Circuit

Input Pulse Levels

0.1 VDD to 0.9 VDD

Input rise and fall times

10 ns

Input and output timing levels

0.5 VDD

Diagram Notes

All start and stop timing parameters apply to both read and write

cycles. Clock specifications are identical for read and write cycles.

Write timing parameters apply to slave address, word address, and

write data bits. Functional relationships are illustrated in the relevant

data sheet sections. These diagrams illustrate the timing parameters

only.

Read Bus Timing

SU:STA

Start

Stop Start

BUF

HIGH

1/fSCL

LOW

Acknowledge

HD:DAT

SU:DAT

SCL

SDA

Write Bus Timing

SU:STO

Start

Stop Start

Acknowledge

HD:DAT

HD:STA

SU:DAT

SCL

SDA

Power Cycle Timing

VDD

2.7V

Can user

access device?

RPU

yes

3.6V

Output

1100



100 pF

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