PIC32MX120F032D datasheet(71/320 Pages) MICROCHIP

71 / 320 page

5280

U1FRML(3)

31:16

—

0000

15:0

—

FRML<7:0>

0000

5290

U1FRMH(3)

31:16

—

0000

15:0

—

FRMH<2:0>

0000

52A0

U1TOK

31:16

—

0000

15:0

—

PID<3:0>

EP<3:0>

0000

52B0

U1SOF

31:16

—

0000

15:0

—

CNT<7:0>

0000

52C0

U1BDTP2

31:16

—

0000

15:0

—

BDTPTRH<7:0>

0000

52D0

U1BDTP3

31:16

—

0000

15:0

—

BDTPTRU<7:0>

0000

52E0

U1CNFG1

31:16

—

0000

15:0

—

—UTEYE

UOEMON

—

USBSIDL

—

UASUSPND 0001

5300

U1EP0

31:16

—

0000

15:0

—

LSPD

RETRYDIS

—

EPCONDIS EPRXEN EPTXEN

EPSTALL

EPHSHK

0000

5310

U1EP1

31:16

—

0000

15:0

—

EPCONDIS EPRXEN EPTXEN

EPSTALL

EPHSHK

0000

5320

U1EP2

31:16

—

0000

15:0

—

EPCONDIS EPRXEN EPTXEN

EPSTALL

EPHSHK

0000

5330

U1EP3

31:16

—

0000

15:0

—

EPCONDIS EPRXEN EPTXEN

EPSTALL

EPHSHK

0000

5340

U1EP4

31:16

—

0000

15:0

—

EPCONDIS EPRXEN EPTXEN

EPSTALL

EPHSHK

0000

5350

U1EP5

31:16

—

0000

15:0

—

EPCONDIS EPRXEN EPTXEN

EPSTALL

EPHSHK

0000

5360

U1EP6

31:16

—

0000

15:0

—

EPCONDIS EPRXEN EPTXEN

EPSTALL

EPHSHK

0000

5370

U1EP7

31:16

—

0000

15:0

—

EPCONDIS EPRXEN EPTXEN

EPSTALL

EPHSHK

0000

5380

U1EP8

31:16

—

0000

15:0

—

EPCONDIS EPRXEN EPTXEN

EPSTALL

EPHSHK

0000

TABLE 4-27:

USB REGISTER MAP(1) (CONTINUED)

Bits

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

Legend:

x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See

Section 11.2 “CLR, SET and INV Registers” for more information.

This register does not have associated SET and INV registers.

This register does not have associated CLR, SET and INV registers.

Reset value for this bit is undefined.

PIC32MX120F032D Datasheet(PDF) 71 Page - Microchip Technology

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