EDJ8232B5MB datasheet(80/142 Pages) ELPIDA

80 / 142 page

EDJ8232B5MB

Data Sheet E1825E30 (Ver. 3.0)

Write Leveling Procedure

Memory controller initiates leveling mode of all DRAMs by setting bit 7 of MR1 to 1. Since the controller levelizes

rank at a time, the output of other rank must be disabled by setting MR1 bit A12 to 1. Controller may assert ODT

after tMOD, time at which DRAM is ready to accept the ODT signal.

Controller may drive DQS low and /DQS high after a delay of tWLDQSEN, at which time DRAM has applied on-die

termination on these signals. After tWLMRD, controller provides a single DQS, /DQS edge which is used by the

DRAM to sample CK driven from controller. tWLMRD timing is controller dependent.

DRAM samples CK status with rising edge of DQS and provides feedback on all the DQ bits asynchronously after

tWLO timing. There is a DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits; there are no read

strobes (DQS, /DQS) needed for these DQs. Controller samples incoming DQ and decides to increment or

decrement DQS delay setting and launches the next DQS, /DQS pulse after some time, which is controller

dependent.

Once a 0 to 1 transition is detected, the controller locks DQS delay setting and write leveling is achieved for the

device. The below figure describes detailed timing diagram for overall procedure and the timing parameters are

shown in below figure.

/CK

Command

ODT

diff_DQS*4

All DQs*1

Notes:1. DDR3 SDRAM drives leveling feedback on all DQs.

2. MRS : Load MR1 to enter write leveling mode.

3. NOP : NOP or deselec

4. diff_DQS is the differential data strobe (DQS, /DQS). Timing reference points are the zero crossing. DQS is

shown with solid line, /DQS is shown with dotted line.

5. CK, /CK : CK is shown with solid dark line, where as /CK is drawn with dotted line.

6. DQS needs to fulfill minimum pulse width requirements tDQSH (min.) and tDQSL (min.) as defined for regular

writes; the max pulse width is system dependent.

tMOD

tWLO

tWLH

tWLS

tWLMRD

tWLO

tWLOE

tDQSL (min.)

tDQSH (min.)

tDQSL (min.)

tDQSH (min.)

tWLDQSEN

MRS

NOP

tWLH

tWLS

Timing Details Write Leveling Sequence

EDJ8232B5MB Datasheet(PDF) 80 Page - Elpida Memory

EDJ8232B5MB Datasheet(HTML) 80 Page - Elpida Memory

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL