MPC8377E datasheet(19/127 Pages) FREESCALE

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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

6.2

DDR1 and DDR2 SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR SDRAM interface.

6.2.1

DDR1 and DDR2 SDRAM Input AC Timing Specifications

This table provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8 V.

This table provides the input AC timing specifications for the DDR1 SDRAM when GVDD(typ) = 2.5 V.

This table provides the input AC timing specifications for the DDR1 and DDR2 SDRAM interface.

Table 18. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

Parameter

Symbol

Min

Max

Unit

AC input low voltage

VIL

—MVREF – 0.25

AC input high voltage

VIH

MVREF + 0.25

—

Table 19. DDR1 SDRAM Input AC Timing Specifications for 2.5-V Interface

Parameter

Symbol

Min

Max

Unit

AC input low voltage

VIL

—MVREF – 0.31

AC input high voltage

VIH

MVREF + 0.31

—

Table 20. DDR1 and DDR2 SDRAM Input AC Timing Specifications

Parameter

Symbol

Min

Max

Unit

Note

Controller skew for MDQS-MDQ/MECC/MDM

400 MHz data rate

333 MHz data rate

266 MHz data rate

tCISKEW

–500

–750

500

750

1, 2

—

Note:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQSn and any corresponding bit that

will be captured with MDQS

n. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be

determined by the following equation: tDISKEW = ±[T/4 – |tCISKEW|] where T is the MCK clock period and |tCISKEW| is the

absolute value of tCISKEW.

3. This specification applies only to DDR2 interface.

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