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SPC564L54L5 Datasheet(PDF) 121 Page - STMicroelectronics |
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SPC564L54L5 Datasheet(HTML) 121 Page - STMicroelectronics |
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121 / 160 page  SPC56XL60/54 Electrical characteristics Doc ID 15457 Rev 8 121/160 5T64KPPERASE *(5) 64 KB block pre-program and erase time 800 1800 900 5000 ms 6T128KPPERASE *(5) 128 KB block pre-program and erase time 1500 2600 1300 7500 ms 7T256KPPERASE *(5) 256 KB block pre-program and erase time 3000 5200 2600 15000 ms 1. Typical program and erase times represent the median performance and assume nominal supply values and operation at 25C. These values are characterized, but not tested.I 2. Initial Max program and erase times provide guidance for time-out limits used in the factory and apply for < 100 program/erase cycles, nominal supply values and operation at 25C. These values are verified at production test. 3. Lifetime Max program and erase times apply across the voltage, temperature, and cycling range of product life. These values are characterized, but not tested. 4. Program times are actual hardware programming times and do not include software overhead. 5. Program times are actual hardware programming times and do not include software overhead. Table 27. Flash memory program and erase electrical specifications No. Symbol Parameter Typ (1) Factory Avg Initial Max (2) Lifetime Max(3) Unit Table 28. Flash memory timing Symbol Parameter Value Unit Min Typ Max TRES D Time from clearing the MCR-ESUS or PSUS bit with EHV = 1 until DONE goes low —— 100 ns TDONE D Time from 0 to 1 transition on the MCR-EHV bit initiating a program/erase until the MCR-DONE bit is cleared —— 5 ns TPSRT D Time between program suspend resume and the next program suspend request.(1) 100 — — µs TESRT D Time between erase suspend resume and the next erase suspend request.(2) 10 ms 1. Repeated suspends at a high frequency may result in the operation timing out, and the flash module will respond by completing the operation with a fail code (MCR[PEG] = 0), or the operation not able to finish (MCR[DONE] = 1 during Program operation). The minimum time between suspends to ensure this does not occur is TPSRT. 2. If Erase suspend rate is less than TESRT, an increase of slope voltage ramp occurs during erase pulse. This improves erase time but reduces cycling figure due to overstress |
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