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ST10F280 Datasheet(PDF) 161 Page - STMicroelectronics

Part # ST10F280
Description  16-bit MCU with MAC unit, 512 Kbyte Flash memory and 18 Kbyte RAM
PDF  239 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
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ST10F280 Datasheet(HTML) 161 Page - STMicroelectronics

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ST10F280
CAN modules
Doc ID 8673 Rev. 3
161/239
As for all other interrupts, the interrupt request flag XP0IR/XP1IR in register XP0IC/XP1IC is
cleared automatically by hardware when this interrupt is serviced (either by standard
interrupt or PEC service).
Note:
As a rule, CAN interrupt requests can be serviced by a PEC channel. However, because
PEC channels only can execute single predefined data transfers (there are no conditional
PEC transfers), PEC service can only be used, if the respective request is known to be
generated by one specific source, and that no other interrupt request will be generated in
between. In practice this seems to be a rare case.
Since an interrupt request of the CAN Module can be generated due to different conditions,
the appropriate CAN interrupt status register must be read in the service routine to
determine the cause of the interrupt request. The Interrupt Identifier INTID (a number) in the
Interrupt Register indicates the cause of an interrupt. When no interrupt is pending, the
identifier will have the value 00h. If the value in INTID is not 00h, then there is an interrupt
pending. If bit IE in the Control Register is set, also the interrupt line to the CPU is activated.
The interrupt line remains active until either INTID gets 00h (after the interrupt requester has
been serviced) or until IE is reset (if interrupts are disabled).
The interrupt with the lowest number has the highest priority. If a higher priority interrupt
(lower number) occurs before the current interrupt is processed, INTID is updated and the
new interrupt overrides the last one. The Table 31 lists the valid values for INTID and their
corresponding interrupt sources.
Interrupt Register
Address:
0xEF02h / 0xEE02h XReg
Reset:
0x--XXh
Type:
R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
INTID
R
INTID Interrupt Identifier
This number indicates the cause of the interrupt. When no interrupt is pending, the value will
be “00”.
Table 31.
INTID values and corresponding interrupt sources
INTID
Cause of the Interrupt
00
Interrupt Idle: There is no interrupt request pending.
01
Status Change Interrupt: The CAN controller has updated (not necessarily changed) the
status in the Control Register. This can refer to a change of the error status of the CAN
controller (EIE is set and BOFF or EWRN change) or to a CAN transfer incident (SIE must
be set), like reception or transmission of a message (RXOK or TXOK is set) or the
occurrence of a CAN bus error (LEC is updated). The CPU may clear RXOK, TXOK, and
LEC, however, writing to the status partition of the Control Register can never generate or
reset an interrupt. To update the INTID value the status partition of the Control Register
must be read.



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