PXR40 datasheet(91/100 Pages) FREESCALE

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Electrical characteristics

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

The DSPI in this device can be configured to serialize data to an external device that implements the Microsecond Bus protocol.

DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) for data and clock signals to improve high

speed operation.

Data Setup Time for Inputs

Master (MTFE = 0)

Slave

Master (MTFE = 1, CPHA = 0)8

Master (MTFE = 1, CPHA = 1)

tSUI

—

Data Hold Time for Inputs

Master (MTFE = 0)

Slave

Master (MTFE = 1, CPHA = 0)8

Master (MTFE = 1, CPHA = 1)

tHI

–3

—

Data Valid (after SCK edge)

Master (MTFE = 0)

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

tSUO

—

Data Hold Time for Outputs

Master (MTFE = 0)

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

tHO

–5

2.5

–5

—

1 DSPI timing specified at V

DD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, and TA =TL to TH

2 Speed is the nominal maximum frequency of platform clock (f

platf). Max speed is the maximum speed allowed including

frequency modulation (FM). 270 MHz parts allow for 264 Mhz for system core clock (fsys) + 2% FM.

3 The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated

based on two devices communicating over a DSPI link.

4 The actual minimum SCK cycle time is limited by pad performance.

5 The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK].

6 The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC].

7 For example, external master should start SCK clock not earlier than 3 system clock periods after assertion SS

8 This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.

Table 38. DSPI LVDS timing1, 2

1 These are typical values that are estimated from simulation.

2 See DSPI LVDS Pad related data in Table 14.

Characteristic

Symbol

Min

Max

Unit

LVDS Clock to Data/Chip Select Outputs

tLVDSDATA

–0.25 ×

tSCYC

+0.25 ×

tSCYC

Table 37. DSPI timing1 2 (continued)

Spec

Characteristic

Symbol

Peripheral Bus Freq: 132 MHz

Unit

Min

Max

PXR40 Datasheet(PDF) 91 Page - Freescale Semiconductor, Inc

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