PXR40PB datasheet(4/23 Pages) FREESCALE

4 / 23 page

PXR40 Product Brief, Rev. 1

Preliminary—Subject to Change Without Notice

Features

Freescale Semiconductor

2.2

PXR40 block diagram

Figure 1 shows a top-level block diagram of the PXR40 microcontrollers.

Figure 1. PXR40 block diagram

Crossbar Switch (XBAR)

Memory Protection Unit (MPU)

Data and Instruction System

PBRIDGE A

PXR40 Block Diagram

System

Integration

Interrupt

Controller

Osc/PLL

SPE2

Debug

Nexus

JTAG

IEEE

ISTO

5001™-2003

2 x eDMA

64- and

32-ch

e200z7

Superscalar

CPU

PBRIDGE B

256 KB

SRAM

w/ECC

(32 KB S/B)

4MB

Flash

w/ECC

Main Memory System

SIU

Timed I/O System

Boot Assist

Module

(BAM)

Data

24K

Code

RAM

eMIOS

32-ch

eTPU2

32-ch

eTPU2

32-ch

4 x

CAN

3 x

UART/

4 x

SPI

4 x

Dec

Fil

64-ch

QUAD

ADCi

Communications

FlexRay™

Controller

ADC

– Analog-to-digital converter

ADCi

– ADC interface

AIPS

– Peripheral I/O bridge

AMux

– Analog multiplexer

CAN

– Controller area network

DECFIL– Decimation filter

EBI

– External bus interface

ECSM – Error correction status module

eDMA2 – Enhanced direct memory access

eMIOS – Enhanced modular I/O system

eQADC – Enhanced queued A/D converter module

eTPU2 – Enhanced time processing unit 2

MMU

– Memory management unit

MPU

– Memory protection unit

PBRIDGE – Peripheral I/O bridge

S/B

– Stand-by

SIU

– System integration unit

SPE2

– Signal processing engine 2

SPI

– Serial peripheral interface controller

SRAM

– General-purpose static RAM

UART/LIN – Universal asynchronous receiver/transmitter/

local interconnect network

VLE

– Variable length instruction encoding

LIN

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