Features

PXR40 Product Brief, Rev. 1

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

7

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Multiple-mapping support and mapping-based block access timing (0–31 additional cycles)

allowing use for emulation of other memory types

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Software programmable block program/erase restriction control

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ECC with single-bit correction, double-bit detection

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Minimum program size is two consecutive 32-bit words, aligned on a 0-modulo-8 byte address

(due to ECC)

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Embedded hardware program and erase algorithm

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Erase suspend, program suspend and erase-suspended program

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Shadow information stored in non-volatile shadow block

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Independent program/erase of the shadow block

2.5.3

General-purpose static RAM (SRAM)

The PXR40 SRAM module provides an internal general-purpose 256 KB memory block. The SRAM

controller includes these features:

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Supports read/write accesses mapped to the SRAM memory from any master

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32 KB block powered by separate supply for standby operation (contents retained)

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Byte, halfword, word, and doubleword addressable

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ECC performs single-bit correction, double-bit detection on 64-bit data elements

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ECC single-bit error corrections are optionally visible to software

2.5.4

Error correction status module (ECSM)

The error correction status module (ECSM) provides the following:

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Status information regarding platform memory errors reported by error detection code (EDC) and

error correcting code (ECC) hardware

— Single-bit correction reporting for SRAM and flash memory

— Multi-bit error reporting

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Includes facilities to allow CPU software to test the error ECC and EDC operation for on-chip

memories by supporting injection of arbitrary error patterns

2.5.5

Enhanced modular input output system (Timer—eMIOS)

The eMIOS module provides the functionality to generate or measure time events. A unified channel (UC)

module is employed that provides a superset of the functionality of all of the MIOS channels used on

MPC5500 family devices, while providing a consistent user interface. This allows more flexibility as each

unified channel can be programmed for different functions in different applications. To identify as many

as two timed events, each UC contains two comparators, a time base selector and registers. This structure

is able to produce match-events, which can be configured to measure or generate a waveform.