PXR40 Product Brief, Rev. 1

Preliminary—Subject to Change Without Notice

Features

Freescale Semiconductor

6

— Minimizes impact on performance

•

Six read and three write operations per clock

— Integrates a pair of integer execution units, a branch control unit, instruction fetch unit and

load/store unit, and a multi-ported register file

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Branch target prefetching performed by the branch unit allows single-cycle branches in many cases

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16 KB instruction cache and 16 KB data cache, both supporting error detection hardware.

•

Memory management unit (MMU) with 64-entry fully-associative translation look-aside buffer (TLB)

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Nexus Class 3+ module

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Supports non-maskable interrupt (completely un-maskable and not guaranteed to be recoverable)

and critical interrupt (an interrupt that can be masked and is guaranteed to be recoverable) sources

— Routed from a single package pin, via edge detection logic in the SIU, to the CPU

•

An additional Wait for Interrupt instruction:

— Used in conjunction with low power STOP mode

— Instruction stops the system clock

— An external interrupt source or the system wake-up timer restart the system clock, allowing the

CPU to service the interrupt

•

Includes multiple input signature register (MISR) hardware which can be accessed by software to

implement CPU self test functionality

2.5.2

On-chip flash memory

The PXR40 flash memory module provides the following:

•

4 MB of programmable, non-volatile, flash memory

— Nonvolatile memory (NVM) can be used for instruction and/or data storage

•

A fetch accelerator optimizes the performance of the flash memory array to match the CPU

architecture

— Architected to optimize the performance of the flash memory with the CPU to provide

single-cycle random access to the flash memory when in full clock mode, and two-cycle access

when in double clock mode

— Configurable read buffering and line prefetch support

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An interface between the system bus and a dedicated flash memory array controller

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Supports a 64-bit data bus width at the system bus port for CPU loads, DMA transfers and CPU

instruction fetch

— Byte, halfword, word, and doubleword reads are supported

— Only aligned word and doubleword writes are supported

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Hardware and software configurable read and write access protections on a per-master basis

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Pipelined interface to the flash memory array controller allowing overlapped accesses to proceed

in parallel for interleaved or pipelined flash memory array designs

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Configurable access timing allowing use in a wide range of system frequencies