PXR40 Product Brief, Rev. 1

Preliminary—Subject to Change Without Notice

Features

Freescale Semiconductor

10

The following features are implemented:

•

Four independent timer channels

•

Each channel includes 32-bit wide down counter with automatic reload

•

Three channels clocked from system clock

•

One channel clocked from crystal clock (wake-up timer)

•

Wake-up timer remains active when system enters stop mode. Used to restart system clock after

predefined time-out period

•

Each channel can optionally generate interrupt request when timer reaches zero

•

Channels can optionally produce trigger event when timer reaches zero (used to trigger eQADC

queues)

2.5.9

System timer module (STM)

The system timer module (STM) is a 32-bit timer designed to support commonly required operating

system and application software timing functions. The STM includes a 32-bit up counter and four 32-bit

compare channels with a separate interrupt source for each channel.

The following features are implemented:

•

One 32-bit up counter with 8-bit prescaler

•

Four 32-bit compare channels

•

Independent interrupt source for each channel

•

Counter can be stopped in debug mode

2.5.10

Enhanced queued analog to digital converter (eQADC)

The enhanced queued analog to digital converter (eQADC) block provides accurate and fast conversions

for a wide range of applications. The two eQADCs on the PXR40 provide a parallel interface to four

on-chip analog to digital converters (ADC), and a single-master to single-slave serial interface to an

off-chip external device.

The ADCs include features designed to allow the direct connection of high impedance acoustic sensors

that might be used in a system for detecting engine knock. These features include differential inputs;

integrated variable gain amplifiers for increasing the dynamic range; programmable pullup and pulldown

resistors for biasing and sensor diagnostics.

eQADC_B also integrates four programmable decimation filters capable of taking in ADC conversion

results at a high rate, passing them through a hardware low-pass filter, then down-sampling the output of

the filter and feeding the lower sample rate results to the result FIFOs. This allows the ADCs to sample

the sensor at a rate high enough to avoid aliasing of out-of-band noise, while providing a reduced sample

rate output to minimize the amount of DSP processing bandwidth required to fully process the digitized

waveform.

The eQADCs provide the following features:

•

Quad on-chip ADCs