OR3C80 datasheet(14/210 Pages) AGERE

14 / 210 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Programmable Logic Cells (continued)

Table 4. Control Input Functionality

Mode

CLK

LSR

ASWE

SEL

Logic

CLK to all latches/

FFs

LSR to all latches/

FFs, enabled per nib-

ble and for ninth FF

CE to all latches/FFs,

selectable per nibble

and for ninth FF

CE to all latches/FFs,

selectable per nibble

and for ninth FF

Select between LUT

input and direct input

for eight latches/FFs

Half Logic/

Half Ripple

CLK to all latches/

FFs

LSR to all latches/FF,

enabled per nibble

and for ninth FF

CE to all latches/FFs,

selectable per nibble

and for ninth FF

Ripple logic control

input

Select between LUT

input and direct input

for eight latches/FFs

Ripple

CLK to all latches/

FFs

LSR to all latches/

FFs, enabled per nib-

ble and for ninth FF

CE to all latches/FFs,

selectable per nibble

and for ninth FF

Ripple logic control

input

Select between LUT

input and direct input

for eight latches/FFs

Memory

(RAM)

CLK to RAM

Port enable 2

Port enable 1

Write enable

Not used

Memory

(ROM)

Optional for sync.

outputs

Not used

Logic Mode

The PFU diagram of Figure 3 represents the logic

mode of operation. In logic mode, the eight LUTs are

used individually or in flexible groups to implement user

logic functions. The latches/FFs may be used in con-

junction with the LUTs or separately with the direct

PFU data inputs. There are three basic submodes of

LUT operation in PFU logic mode: F4 mode, F5 mode,

and softwired LUT (SWL) mode. Combinations of these

submodes are possible in each PFU.

F4 mode, shown simplified in Figure 4, illustrates the

uses of the basic 4-input LUTs in the PFU. The output

of an F4 LUT can be passed out of the PFU, captured

at the LUTs associated latch/FF, or multiplexed with the

adjacent F4 LUT output using one of the F5[A:D] inputs

to the PFU. Only adjacent LUT pairs (K0 and K1, K2

and K3, K4 and K5, K6 and K7) can be multiplexed, and

the output always goes to the even-numbered output of

the pair.

The F5 submode of the LUT operation, shown simpli-

fied in Figure 4, indicates the use of 5-input LUTs to

implement logic. 5-input LUTs are created from two

4-input LUTs and a multiplexer. The F5 LUT is the

same as the multiplexing of two F4 LUTs described

previously with the constraint that the inputs to the F4

LUTs be the same. The F5[A:D] input is then used as

the fifth LUT input. The equations for the two F4 LUTs

will differ by the assumed value for the F5[A:D] input,

one F4 LUT assuming that the F5[A:D] input is zero,

and the other assuming it is a one. The selection of the

appropriate F4 LUT output in the F5 MUX by the

F5[A:D] signal creates a 5-input LUT. Any combination

of F4 and F5 LUTs is allowed per PFU using the eight

16-bit LUTs. Examples are eight F4 LUTs, four F5

LUTs, and a combination of four F4 plus two F5 LUTs.

5-5970(F)

Figure 4. Simplified F4 and F5 Logic Modes

F5D

F5C

F5B

F5A

K7/K6

K5/K4

K3/K2

K1/K0

F5 MODE

MULTIPLEXED F4 MODE

F4 MODE

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