OR3C80 datasheet(64/210 Pages) AGERE

64 / 210 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Microprocessor Interface (MPI)

The Series 3 FPGAs have a dedicated synchronous

microprocessor interface function block (see

Figure 42). The MPI is programmable to operate with

PowerPC MPC800 series microprocessors and Intel*

i960* J core processors; see Table 16 and Table 17,

respectively, for compatible processors. The MPI imple-

ments an 8-bit interface to the host processor (

Pow-

erPC or i960) that can be used for configuration and

readback of the FPGA as well as for user-defined data

processing and general monitoring of FPGA function.

In addition to dedicated-function registers, the micro-

processor interface allows for the control of up to 16

user registers (RAM or flip-flops) in the FPGA logic. A

synchronous/asynchronous handshake procedure is

used to control transactions with user logic in the FPGA

array. There is also capability for the FPGA logic to

interrupt the host processor either by a hard interrupt or

by having the host processor poll the microprocessor

interface.

The control portion of the microprocessor interface is

available following powerup of the FPGA if the mode

pins specify MPI mode, even if the FPGA is not yet con-

figured. The mode pin (M[2:0]) settings can be found in

the FPGA Configuration Modes section of this data

sheet, and the setup and use of the MPI for configura-

tion is discussed in the MPI Setup and Control subsec-

tion. For postconfiguration use, the MPI must be

included in the configuration bit stream by using an MPI

library element in your design from the

ORCA macro

library, or by setting the MP_USER bit of the MPI con-

figuration control register prior to the start of configura-

tion (MPI registers are discussed later).

Intel and i960 are registered trademarks of Intel Corporation.

5-5806(F)

Figure 42. MPI Block Diagram

DONE

RD_DATA

INIT

D7IN

D7OUT

D6IN

D6OUT

D5IN

D5OUT

D4IN

D4OUT

D3IN

D3OUT

D2IN

D2OUT

D1IN

D1OUT

D0IN

D0OUT

ORCA 3C/Txxx MPI

STATUS

SCRATCHPAD

READBACK

DATA REGISTER

READBACK

ADDR REGISTER

CONTROL

REGISTERS

PART ID

REGISTERS

RESET

RD_CFG

PRGM

GSR

IRQ

TO GSR BLOCK

TO FPGA

ROUTING

USER_START

USER_END

WR_CTRL

A[3:0]

RDYRCV

CLK

ADS

ALE

W/R

i960 LOGIC

RD/WR

CLKOUT

POWERPC LOGIC

CS0

CS1

CCLK

MPI_IRQ

MPI_ACK

MPI_CLK

MPI_STRB

MPI_ALE

MPI_RW

MPI_B1

TO FPGA

ROUTING

D[7:0]IN

D[7:0]OUT

DEVICE PAD

I/O BUFFER

OR3C80 Datasheet(PDF) 64 Page - Agere Systems

OR3C80 Datasheet(HTML) 64 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL