OR3C80 datasheet(45/210 Pages) AGERE

45 / 210 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Programmable Input/Output Cells

(continued)

PIC Architectural Description

The PIC architecture as seen in

ORCA Foundry is

shown in Figure 27. The figure is the left PIC of a PIC

pair on the top edge of a Series 3 array. Both PICs in a

pair are similar, with the differences mainly lying in the

connections between the PIC switching segments

(pSW), the IN2 connections across PIC boundaries,

and the system clock spine driver residing in only one

PIC of a pair.

A. This is a programmable input/output (PIO). There

are four PIOs per PIC. The PIOs contain the PIC

logic and I/O buffers.

B. This is the PIC output switching block. It connects

the PIC switching segments and local clock lines to

the PIO output and control signals.

C. This is the system clock spine switching block and

buffer. There is only one system clock spine per pair

of PICs. Its inputs can come from the PIC switching

segments or any of the eight PIO inputs in a PIC

pair.

D.PIC switching segments (pSW). These routing seg-

ments are used to interconnect routing resources

within the PIC and to a lesser degree, between

PICs.

E. px1 routing segments. The PIC x1 routing seg-

ments traverse one PIC and break at a CIP in the

middle of each PIC.

F. px2 routing segments. The PICs have routing that

traverses two PICs between breaks. The breaks are

staggered among the five px2 segments.

G. px5 routing segments. Each of the ten PIC x5 rout-

ing segments traverses five PICs in between breaks

at a CIP. Two px5 segments break in each PIC.

H. pxH routing segments. The eight PIC xH routing

segments traverse half of the array and break at

CIPs in the interquad routing region that is in the

middle of the array.

(Not used intentionally for clarity.)

J. pxL routing segments. The PIC long lines run the

entire length of the side of the array.

K.x5 routing segments from the adjacent PLC routing.

L.xL routing segments from the adjacent PLC routing.

M.x1 routing segments from the adjacent PLC routing.

N.Switching segments from the adjacent PLC routing.

O.xH routing segments from the adjacent PLC routing.

P. BIDI routing segments from the adjacent PLC rout-

ing.

Q. These are the IN2 routing segments. There is one

IN2 line from each PIO, and all eight IN2 lines from

each PIC pair are present in both PICs of a pair.

R. These CIPs connect the IN1 and IN2 routing seg-

ments from the PIOs to the PIC switching seg-

ments.

S. These CIPs break the PIC switching segments at

the interface between a PIC pair.

T. These CIPs connect adjacent PLC routing

resources to the PIC switching segments.

U. These CIPs connect inter-PIC routing with the PIC

switching segments.

V. These CIPs break the px1, px2, and px5 routing at

the middle of a PIC. The px2 and px5 CIP place-

ment varies depending on the PLC.

W. These mutually exclusive buffers can drive one long

line signal onto a PIC local clock routing segment.

X. These mutually exclusive buffers can select a

source from one of the local system clock routes to

drive the PIO 3-state control signal.

Y. These are the four local system clock routing seg-

ments. Two come from connections within the PIC,

one from the other PIC in the pair, and one from the

adjacent PLC.

Z. These mutually exclusive buffers allow a signal on

the PIC switching segments to be routed to a sys-

tem clock spine or to a PIO system clock.

AA. ExpressCLK routing line.

AB.System clock spine.

AC. These various groups of CIPs connect routing

resources from the adjacent PLC to the inter-PIC

routing resources.

AD. These buffers provide connectivity between the

PLC xL (xH) lines and the PIC xL (xH) lines or

connectivity between one of the IN2 routing seg-

ments and the PIC and/or PLC xL (xH) routing

segments.

AE. These mutually exclusive buffers and CIPs provide

connectivity to the PLC xL and xH lines from one

of the IN2 input segments.

AF. These buffers allow the IN2 signals to drive onto

the BIDI routing of the adjacent PLC, or the BIDI

routing of the adjacent PLC, and the PIC switching

segments and/or PIC half lines may be connected.

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