OR3C80 datasheet(71/210 Pages) AGERE

71 / 210 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Microprocessor Interface (MPI) (continued)

Device ID Registers

The MPI device ID is broken into four registers holding 1 byte each. The device ID that is available through the MPI

is the same as the boundary-scan ID code, except that the device ID in the MPI has a reverse bit order. There is no

means to overwrite any of the device ID as can be done with the boundary-scan ID, but the MPI scratchpad register

can be used as a personalization register. The format for the entire device ID is shown below followed by family and

device values and the partitioning of the device ID into the four device ID registers.

Table 23. Device ID Code

* PLC array size of FPGA.

Table 24 shows the family and device values for all parts covered by this data sheet.

Table 24. Series 3 Family and Device ID Values

Table 25 describes the device IDs for all parts covered by this data sheet as they are partitioned into the four regis-

ters found in the MPI.

Table 25. ORCA Series 3 Device ID Descriptions

Version

Part*

Family

Manufacturer

MSB

4 bits

10 bits

6 bits

11 bits

1 bit

Example: (First version of Lucent’s OR3C55)

0000 0100100000 110000 00000011101 1

Part Name

Family ID

(Hex)

Device ID

(Hex)

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

Device ID Register 1

Bit 0

Logic 1. This bit is always a one.

Bits [7:1]

0011101, the 7 least significant bits of the Lucent Technologies manufacturer ID.

Device ID Register 2

Bits [3:0]

0000, the 4 most significant bits of the Lucent Technologies manufacturer ID.

Bits [7:4]

The 4 least significant bits of the 10-bit part number.

Device ID Register 3

Bits [5:0]

The 6 most significant bits of the 10-bit part number.

Bits [7:6]

The 2 least significant bits of the device family code.

Device ID Register 4

Bits [3:0]

The 4 most significant bits of the device family code.

Bits [7:4]

The 4-bit device version code.

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