QG5000XSL9TH datasheet(13/458 Pages) INTEL

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Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet

Introduction

The Intel® 5000X chipset is designed for systems based on the Dual-Core Intel®

Xeon® 5000 sequence and supports a FSB frequency up to 1333 MTS. The Intel 5000X

chipset contains two main components: Memory Controller Hub (MCH) for the host

bridge and the I/O controller hub for the I/O subsystem. The Intel 5000X chipset uses

the Intel® 631xESB/632xESB I/O Controller Hub for the I/O Controller Hub. This

document is the datasheet for the Intel 5000X chipset Memory Controller Hub (MCH)

components.

The Intel 5000X chipset is packaged in a 1432 pin FCBGA package with pins on

1.092 mm (37 mil) centers. The overall package dimensions are 42.5 mm by 42.5 mm.

The Intel 5000 Series chipset platform supports the Dual-Core Intel® Xeon® 5000

series (1066 MHz with 2 MB L2 cache on 65nm process in a 771-land, FC-LGA4 (Flip

Chip Land Grid Array 4) package and the Dual-Core Intel® Xeon® 5100 series

(1333 MHz with 4 MB shared L2 cache) on 65nm process in a 771-land, FC-LGA4 (Flip

Chip Land Grid Array 4) package. This package uses the matching LGA771 socket. The

surface mount, LGA771 socket supports Direct Socket Loading (DSL). The Dual-Core

Intel Xeon 5000 sequence (1066/1333 MHz) returns a processor signature of 0F5xh

where x is the stepping number when the CPUID instruction is executed with EAX=1.

Note:

Unless otherwise specified, the term processor in this document refers to the

Dual-Core Intel Xeon 5000 sequence processors at both 1066 MHz with 2 MB L2 cache

and 1333 MHz with 4 MB shared L2 cache on 65nm process in the 771-pin FC-LGA4

package.

1.1

Terminology

This section provides the definitions of some of the terms used in this document.

Table 1-1.

General Terminology (Sheet 1 of 7)

Terminology

Description

Agent

A logical device connected to a bus or shared interconnect that can either initiate

accesses or be the target of accesses. Each thread executing within a processor is a

unique agent.

aka

also known as

Asserted

Asserted Signal is set to a level that represents logical true. For signals that end with

“#” this means driving a low voltage. For other signals, it is a high voltage.

Atomic operation

A series of operations, any one of which cannot be observed to complete unless all are

observed to complete.

AGP

Accelerated Graphics Port. In this document AGP refers to the AGP/PCI interface that

is in the MCH. The MCH AGP interface supports only 0.8 V/1.5 V AGP 2.0/AGP 3.0

compliant devices using PCI (66 MHz), AGP 1X (66 MHz), 4X (266 MHz), and 8X (533

MHz) transfers. MCH does not support any 3.3 V devices. For AGP 2.0, PIPE# and SBA

addressing cycles and their associated data phases are generally referred to as AGP

transactions. FRAME# cycles are generally referred to as AGP/PCI transactions

Bank

DRAM chips are divided into multiple banks internally. Commodity parts are all 4 bank,

which is the only type the MCH supports. Each bank acts somewhat like a separate

DRAM, opening and closing pages independently, allowing different pages to be open

in each. Most commands to a DRAM target a specific bank, but some commands (that

is, Precharge All) are targeted at all banks. Multiple banks allows higher performance

by interleaving the banks and reducing page miss cycles.

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