QG5000XSL9TH datasheet(39/458 Pages) INTEL

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Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet

Signal Description

Table 2-4 summarizes the Product Name Initialization timings.

2.10.3

Miscellaneous Requirements and Limitations

• Power rails and stable BUSCLK, FBD{0/1}CLK, and PECLK master clocks remain

within specifications through all but power-up reset.

• Frequencies (for example, 266 MHz) described in this chapter are nominal. The

Intel® 5000P chipset MCH reset sequences must work for the frequency of

operation range specified in the Clocking chapter.

• Hard Reset can be initiated by code running on a processor, JTAG, SMBus, or PCI

agents.

• Hard Reset is not guaranteed to correct all illegal configurations or malfunctions.

Software can configure sticky bits in the Intel 5000P chipset MCH to disable

interfaces that will not be accessible after Hard Reset. Signaling errors or protocol

violations prior to reset (from processor bus, FB-DIMM, or PCI Express) may hang

interfaces that are not cleared by Hard Reset.

• System activity is initiated by a request from a processor bus. No I/O devices will

initiate requests until configured by a processor to do so.

• The FB-DIMM channels will be enabled for packet levelization (Intel 5000P

MCH.FBDST.STATE=“Ready” or “RecoveryReady” state) upon completion of a hard

reset. Software should inspect the Intel 5000P chipset MCH.FBDST.STATE

configuration bits to determine which FB-DIMM channels are available.

• The default values of the POC configuration register bits do not require any

processor request signals to be asserted when PWRGOOD is first asserted.

Software sets these configuration registers to define these values, then initiates a

hard reset that causes them to be driven during processor RESET# signal

assertion.

• Cleanly aborting an in-progress SPD command during a PWRGOOD deassertion is

problematic. No guarantee can be issued as to the final state of the EEPROM in this

situation. The Intel® 5000P MCH cannot meet the SPD data tSU,STO timing

specification. Since the Intel® 5000P MCH floats the data output into a pull-up on

the platform, a read will not degrade to a write. However, if the PWRGOOD

deassertion occurs after the EEPROM has received the write bit, the data will be

corrupted. The platform pull-up must be strong enough to complete a low-to-high

transition on the clock signal within tR = 1 microsecond (ATMEL AT24C01 timing

specification) after deassertion of PWRGOOD to prevent clock glitches. Within these

constraints, an in-progress write address will not be corrupted.

Table 2-4.

Critical Intel® 5000P Initialization Timings

Sequence

Started by

Maximum Length

Covered by

Timing

parameter

Intel® 5000P chipset Core,

FSB, FB-DIMM PLL lock

Stable power and master clock

666,667 333 MHz cycles

Intel® 5000P MCH PCI Express

PLL lock

Stable power and master clock

200,000 100 MHz cycles

Array initialization

Synchronized RESETI#

Deassertion

200 cycles

T17

Fuse download

PWRGOOD Assertion

333,333 333 MHz cycles

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