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QG5000XSL9TH Datasheet(PDF) 52 Page - Intel Corporation |
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QG5000XSL9TH Datasheet(HTML) 52 Page - Intel Corporation |
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52 / 458 page ![]() Register Description 52 Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet 3.5.2 CFGDAT: Configuration Data Register CFGDAT provides data for the 4 bytes of configuration space defined by CFGADR. This register is only accessed if there is an access to I/O address, CFCh on the processor bus and CFGADR.CFGE (configuration enable) bit is set. The byte enables with the I/O access define how many configuration bytes are accessed. 3.6 MCH Fixed Memory Mapped Registers These registers are mapped into the fixed chipset specific range located from FE60 0000h - FE6F FFFFh.These appear at fixed addresses to support the boot process. These registers also appear in the regular PCI Express configuration space. The following table defines the memory address of the registers in this region. Table 3-6. I/O Address: CFCh Bit Attr Default Description 31:0 RW 0 Configuration Data Window The data written or read to the configuration register (if any) specified by CFGADR Table 3-7. Mapping for Fixed Memory Mapped Registers Register Memory Address BOFL0 FE60_C000 BOFL1 FE60_C400 BOFL2 FE60_C800 BOFL3 FE60_CC00 SPAD0 FE60_D000 SPAD1 FE60_D400 SPAD2 FE60_D800 SPAD3 FE60_DC00 SPADS0 FE60_E000 SPADS1 FE60_E400 SPADS2 FE60_E800 SPADS3 FE60_EC00 AMBASE[31:0] FE61_4800 AMBASE[63:32] FE61_4C00 HECBASE FE61_6400 |
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