PIC16F1459-ESSQTP datasheet(311/418 Pages) MICROCHIP

311 / 418 page

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 311

PIC16(L)F1454/5/9

26.2.2.1

Internal Transceiver

The USB peripheral has a full-speed and low-speed

USB 2.0 capable transceiver internally built-in and

connected to the SIE. The internal transceiver is

enabled when the USBEN bit of the USBCON register

is set. Full-speed operation is selected by setting the

FSEN bit of the UCFG register.

The on-chip USB pull-up resistors are controlled by the

UPUEN bit of the USFG register. The pull-up resistors

can only be active when the USBEN bit of the USBCON

The internal USB transceiver is powered from the

VUSB3V3 pin. In order to meet USB signaling level

specifications, VUSB3V3 must be supplied with a voltage

source between 3.0V and 3.6V. The best electrical

signal quality is obtained when a 3.3V supply is used

and locally bypassed with a high quality ceramic

capacitor. The capacitor should be placed as close as

possible to the VUSB3V3 and VSS pins.

The D+ and D- signal lines can be routed directly to

their respective pins on the USB connector or cable (for

hard-wired applications). No additional resistors,

capacitors, or magnetic components are required as

the D+ and D- drivers have controlled slew rate and

output impedance intended to match with the

characteristic impedance of the USB cable. See the

USB specifications for the impedance matching

requirements.

26.2.2.2

Internal Pull-Up Resistors

The PIC® devices have built-in pull-up resistors

designed to meet the requirements for low-speed and

full-speed USB. The UPUEN bit of the UCFG register

enables the internal pull-ups.

26.2.2.3

Ping-Pong Buffer Configuration

The usage of ping-pong buffers is configured using the

PPB bits of the UCFG register. Refer to Section 26.4.4

“Ping-Pong Buffering”

for a complete explanation of

the ping-pong buffers.

26.2.2.4

Eye Pattern Test Enable

An automatic eye pattern test can be generated by setting

the UTEYE bit of the USFG register. The eye pattern

output is dependent upon the USB modules settings,

which must be configured prior to use. The module must

be enabled for eye pattern output to function.

Once UTEYE is set, the module emulates a switch from

a receive to transmit state and will start transmitting a

J-K-J-K bit sequence (K-J-K-J for full speed). The

sequence will be repeated indefinitely while the Eye

Pattern Test mode is enabled.

This test mode is intended for board verification to aid

with USB certification tests. It is intended to show a

system developer the noise integrity of the USB signals

which can be affected by board traces, impedance

mismatches and proximity to other system components.

It does not properly test the transition from a receive to

a transmit state. Although the eye pattern is not meant

to replace the more complex USB certification test, it

should aid during first order system debugging.

Note:

The VUSB3V3 voltage is supplied.

Note:

The official USB specifications require the

that USB devices must never source any

current onto the VBUS line of the USB

cable. Additionally, USB devices must

never source any current on the D+/D-

data lines when the VBUS is below the

required voltage. In order to meet this

requirement, applications which are not

purely bus powered should monitor the

VBUS line and avoid turning on the USB

module and D+/D- internal pull-up resis-

tors until the VBUS meets requirements.

VBUS can be connected to and monitored

by any 5V tolerant I/O pin for this purpose.

Refer to USB Specification 2.0, 7.2.1 for

information.

Note:

The UTEYE bit should never be set while

the module is connected to an actual USB

system.

PIC16F1459-ESSQTP Datasheet(PDF) 311 Page - Microchip Technology

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