PIC16F1459-ESSQTP datasheet(313/418 Pages) MICROCHIP

313 / 418 page

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 313

PIC16(L)F1454/5/9

26.3

USB RAM

USB data moves between the microcontroller core and

the SIE through the dual-port USB RAM. This is a

special dual access memory that is mapped into a

normal data memory space (Figure 26-3).

The dual-port general purpose memory space is used

specifically for endpoint buffer control. Depending on

the type of buffering being used, all but 8 bytes of Bank

0 may also be available for use as USB buffer space.

Although USB RAM is available to the microcontroller as

data memory, the sections that are being accessed by

the SIE should not be accessed by the microcontroller.

A semaphore mechanism is used to determine the

access to a particular buffer at any given time. This is

discussed in Section 26.4.1.1 “Buffer Ownership”.

FIGURE 26-3:

IMPLEMENTATION OF

USB RAM IN DATA

MEMORY SPACE

26.4

Buffer Descriptors and the Buffer

Descriptor Table

The dual-port general purpose memory space is used

specifically for endpoint buffer control in a structure

known as the Buffer Descriptor Table (BDT). This

provides a flexible method for users to construct and

control endpoint buffers of various lengths and

configuration.

The BDT is composed of Buffer Descriptors (BDs)

which are used to define and control the actual buffers

in the USB RAM space. Each BD, in turn, consists of

four registers:

• BDnSTAT: BD Status register

• BDnCNT: BD Byte Count register

• BDnADRL: BD Address Low register

• BDnADRH: BD Address High register

BDs always occur as a four-byte block in the sequence,

BDnSTAT:BDnCNT:BDnADRL:BDnADRH. The address

of BDnSTAT is accessible in linear data space at 2000h

+ (4n – 1) with n being the buffer descriptor number.

Depending on the buffering configuration used

(Section 26.4.4 “Ping-Pong Buffering”), there are

multiple sets of buffer descriptors. The USB

specification mandates that every device must have

Endpoint 0 with both input and output for initial setup.

Although they can be thought of as Special Function

Registers, the Buffer Descriptor Status and Address

registers are not hardware mapped, as conventional

microcontroller

SFRs

are.

When

the

endpoint

corresponding to a particular BD is not enabled, then its

registers are not used. Instead of appearing as

unimplemented addresses, however, they appear as

available RAM. Only when an endpoint is enabled by

setting the EPINEN bit of the UEPn register does the

memory at those addresses become functional as BD

registers. As with any address in the data memory

space, the BD registers have an indeterminate value on

any device Reset.

An example of a BD for a 64-byte buffer is shown in

Figure 26-4. A particular set of BD registers is only

valid if the corresponding endpoint has been enabled

using the EPINEN bit. All BD registers are available in

USB RAM. The BD for each endpoint should be set up

prior to enabling the endpoint.

512 Byte

CPU Dual-Port RAM

512 Byte

CPU Single-Port RAM

USB RAM Port Remap

(TSTDPEN = 1)

Unimplemented

Read ‘0’

2000h

21FFh

2200h

23FFh

2400h

25FFh

2600h

29AFh

Note:

Wherever BDn is identified within this

document, the n represents one of the

possible BDs.

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