MPC5604E datasheet(63/75 Pages) FREESCALE

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Electrical characteristics

MPC5604E Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

3.18.11 I2C timing

Table 38. I2C SCL and SDA input timing specifications

No.

Symbol

Parameter

Value

Unit

Min

Max

—

D Start condition hold time

—

IP bus cycle1

1 Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device. It is equal to the system clock

(Sys_clk).

—

D Clock low time

—

IP bus cycle1

—

D Data hold time

0.0

—

D Clock high time

—

IP bus cycle1

—

D Data setup time

0.0

—

D Start condition setup time (for repeated start condition only)

—

IP bus cycle1

—

D Stop condition setup time

—

IP bus cycle1

Table 35. I2C SCL and SDA output timing specifications

No.

Symbol

Parameter

Value

Unit

Min

Max

1 Programming IBFD (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings

listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period.

The actual position is affected by the prescale and division values programmed in IFDR.

—

D Start condition hold time

—

IP bus cycle2

2 Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device.

—

D Clock low time

—

IP bus cycle1

3 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL

or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.

—

D SCL/SDA rise time

—

99.6

—

D Data hold time

—

IP bus cycle1

—

D SCL/SDA fall time

—

99.5

—

D Clock high time

—

IP bus cycle1

—

D Data setup time

—

IP bus cycle1

—

D Start condition setup time (for repeated start condition only)

—

IP bus cycle1

—

D Stop condition setup time

—

IP bus cycle1

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